International Business Machines Corporation

Semivation, LLC

Other

Globalfoundries Inc.

International Business Machines Coirporation

Mark Charles Hakey

David V Horak

Steven J Holmes

Toshiharu Furukawa

Charles W Koburger, Iii

Peter H Mitchell

Paul A Rabidoux

Jack Allan Mandelman

William H Ma

Larry Alan Nesbit

Mark Eliot Masters

William R Tonti

Chung H Lam

William H-l Ma

William Hsioh-Lien Ma

Wendell P Noble

James Spiros Nakos

James Gardner Ryan

Thomas Safron Kanarsky

Bruce Bennett Doris

Edmund Juris Sprogis

Gary Bela Bronner

Gerhard Ingmar Meijer

John Gerard Gaudiello

Jeffrey John Welser

Toshijaru Furukawa

Edward J Nowak

Robert H Dennard

James Albert Slinkman

Stephen Ellinwood Luce

James Marc Leas

Niranjan Mohanlal Patel

Ahmad D Katnani

David P Vallett

Leah M P Pastel

Donald Walter Rakowski

Devendra K Sadana

Veeraraghavan S Basker

Ghavam G Shahidi

Keith E Fogel

Tak H Ning

Sanjay C Mehta

Robert K Leidy

Howard L Kalter

Charles Thomas Black

Stanislav Polonsky

Ethan Harrison Cannon

Harold G Linde

David James Frank

Kathryn Wilder Guarini

Song Peng

Richard A Ferguson

William John Adair

Leah Marie Pfeifer Pastel

Henry H K Tang

Keith Raymond Milkove

Patricia McGuiness Marmillion

John Michael Wursthorn

Ronald M Martino

Krishna V Singh

Ramachandra Divakauni

Brent A Anderson

Steven H Voldman

John Atkinson Fifield

Kirk David Peterson

Kenneth Parker Rodbell

Richard Stephan Wise

Wu-Song S Huang

Bomy A Chen

Rajarao Jammy

Jason D Hibbeler

David M Dobuzinsky

Philip Joseph Oldiges

Kuang-Jung Chen

Hongwen Yan

H Bernhard Pogge

Rosemary A Previti-Kelly

Diane Catherine Boyd

William P Parker

Ronald Dennis Rose

Daniel A Corliss

Larry Wissel

Akihisa Sekiguchi

Archibald John Allen

Albert Stephan Bergendahl

Dinesh A Badami

Holger Moritz

Pierre J Bouchard

James M Never

Edward F O'Neil

Roger Andrew Verhelst

Carol Boye

Charles William Koburger Iii

David Vaclav Hotak

David Vaclav Horal

David Vaclav Hofak

John P Wilson

Jack A Mandclman

Stevn J Holmes

David C Horak

A method of fabricating a single-crystal silicon photovoltaic cell includes providing a single-crystal silicon wafer and a structural support member. The single-crystal silicon wafer has a first major surface and a second major surface. Each major surface extends along a major surface plane. The single-crystal silicon wafer has a thickness greater than 100 micrometers and a dimension greater than 50 mm. The method further includes mounting the structural support member to the first major surface or to the second major surface. The method further includes reducing thickness of the single-crystal silicon wafer to a thickness less than or equal to 100 micrometers while the single-crystal silicon wafer is mounted to the structural support member. The method further includes providing the first major surface with a diffusion and a metalization grid and providing the second major surface with a back surface contact.

Thin single-crystal silicon solar cells mounted to a structural support member and method of fabricating

A method of cleaving off a daughter single crystal substrate from a parent single crystal substrate includes providing a stress-mandrel and the parent a single crystal substrate. The parent single crystal substrate has a major surface and an edge surface that intersects the major surface. The major surface extends along a major surface plane. The stress-mandrel has a stress-mandrel coefficient of thermal expansion that is higher than the parent single crystal coefficient of thermal expansion. The method includes bonding the stress-mandrel to the major surface, and cooling the parent single crystal substrate and the stress-mandrel. The cooling of the parent single crystal substrate bonded to the stress-mandrel provides a thermal stress in the parent single crystal substrate sufficient to cleave the parent single crystal substrate. The cleaving extends substantially along a plane parallel to the plane of the major surface. In one embodiment the cleaved daughter substrate was used to make a photovoltaic cell.

Method of cleaving a single crystal substrate parallel to its active planar surface and method of using the cleaved daughter substrate

A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor

Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.

Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules

The invention relates to a design structure, and more particularly, to a design structure for a heavy ion tolerant device, method of manufacturing the same and a structure thereof. The structure includes a first device having a diffusion comprising a drain region and source region and a second device having a diffusion comprising a drain region and source region. The first and second device are aligned in an end-to-end layout along a width of the diffusion of the first device and the second device. A first isolation region separating the diffusion of the first device and the second device.

Structure for heavy ion tolerant device, method of manufacturing the same and structure thereof

The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin.

Radiation hardened FinFET

A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

CMOS gate structures fabricated by selective oxidation

A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

Field effect transistor

A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing.

Chemical and particulate filters containing chemically modified carbon nanotube structures

A design structure including a pair of substantially parallel resistor material lengths separated by a first dielectric are disclosed. The resistor material lengths have a sub-lithographic dimension and may be spacer shaped.

Structure having substantially parallel resistor material lengths

A resistor and design structure including a pair of substantially parallel resistor material lengths separated by a first dielectric are disclosed. The resistor material lengths have a sub-lithographic dimension and may be spacer shaped.

Resistor and design structure having substantially parallel resistor material lengths

A resistor and design structure including at least one resistor material length in a dielectric, each of the least one resistor material length having a sub-lithographic width are disclosed.

Resistor and design structure having resistor material length with sub-lithographic width

A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

Shared gate for conventional planar device and horizontal CNT

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Fairfax, VT, United States of America

Mark Charles Hakey