Altera Corporation

H2o.ai Inc.

Mark Chan

Lin-Shih Liu

Irfan Rahim

Navdeep Gill

Patrick Hall

Jeffrey T Watt

Toan D Do

Yanzhong Xu

Jun Liu

Albert Ratnakumar

Andy Louie Lee

Myron Wai Wong

Shuxian Chen

Shankar Sinha

An indication of a selection of an entry associated with a machine learning model is received. One or more interpretation views associated with one or more machine learning models are dynamically updated based on the selected entry.

Model interpretation

Input data associated with a machine learning model is classified into a plurality of clusters. A plurality of linear surrogate models are generated. One of the plurality of linear surrogate models corresponds to one of the plurality of clusters. A linear surrogate model is configured to output a corresponding prediction based on input data associated with a corresponding cluster. Prediction data associated with the machine learning model and prediction data associated with the plurality of linear surrogate models are outputted.

An integrated circuit includes a buffer circuit, a receiving circuit, and a programmable repeater circuit. The programmable repeater circuit includes a routing input and an enable input. The programmable repeater circuit buffers an input signal received at the routing input from the buffer circuit through a first conductor to generate an output signal that is provided to an input of the receiving circuit through a second conductor only in response to an enable signal at the enable input enabling the programmable repeater circuit.

Programmable repeater circuits and methods

Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

Memory elements with relay devices

A memory cell includes a bistable element and two p-channel transistors (i.e., first and second p-channel transistors). The bistable element includes a plurality of inverting circuits and at least one data storage node. The bistable element may be formed in a first region on the substrate that is partially formed by a p-type diffusion region and an n-type diffusion region. The first and second p-channel transistors are coupled serially. The first p-channel transistor may also have its gate terminal coupled to the at least one data storage node of the bistable element. A method of manufacturing the memory cell includes forming a bistable element having at least first and second data storage nodes, forming a write-only port of the memory cell over an n-type diffusion region and forming a read-only port of the memory cell over a p-type diffusion region.

Memory cells with p-type diffusion read-only port

Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Memory elements with elevated control signal levels for integrated circuits

Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

Integrated circuits with asymmetric pass transistors

Memory elements may be provided that include bi-stable data storage elements based on cross-coupled inverters. A pair of address transistors may be used to implement a differential data writing scheme for the memory elements. One of the address transistors may be coupled between a first data line and a first data storage node in each memory element and another of the address transistors may be coupled between a second data line and a second data storage node. A read circuit may be coupled to the second data storage node. Clear transistors may be interspersed through the array. The clear transistors may help pull the data lines to desired voltages during clear operations. An adjustable power supply may supply a weakened power supply voltage to a pull-up clear transistor and to the first and second inverters during clear operations.

Memory array with distributed clear transistors and variable memory element power supply

Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits

Integrated circuits are provided that have memory elements. The memory elements may be organized in an array. Data such as programmable logic device configuration data may be loaded into the array using read and write control circuitry. Each memory element may store data using a pair of cross-coupled inverters. Power supply circuitry may be used to power the cross-coupled inverters. A positive power supply signal and a ground power supply signal may be provided to the inverters by the power supply circuitry. Each memory element may have an associated clear transistor. A clear control signal may be asserted to turn on the clear transistor when clearing the memory elements. A given one of the inverters in each memory element may be momentarily weakened with respect to the clear transistor in that memory element by using the power supply circuitry to temporarily elevate the ground power supply signal.

Integrated circuits with clearable memory elements

Memory elements for integrated circuit are provided that have efficient transistor layouts. The integrated circuits may be programmable logic device integrated circuits on which memory elements are formed into arrays. Each memory element may have a pair of cross-coupled inverters, an address transistor, and a clear transistor. The transistors in each memory element may be formed from n-type and p-type semiconductor regions that are crossed by only three gate conductor fingers. Programmable transistors on the integrated circuit may be controlled by static output signals from the memory elements. The programmable transistors may be used to form multiplexers. The multiplexers may be formed from n-type regions that are crossed by only three gate fingers each. The gate fingers of the multiplexers may be aligned with the gate fingers of the transistor structures of the memory elements.

Growing community of inventors

San Jose, CA, United States of America

Mark Chan