Arm Limited

Mark Carpenter Glass

James Nolan Hardage

Glen Andrew Harris

A loop buffer is provided with a main storeand an auxiliary store. The main storestores micro-operation instructions. The auxiliary storehas fewer entries than the main storeand stores target addresses for predicted taken branch instructions stored within the main store. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.

Buffer store with a main store and and auxiliary store

A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register

A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register filecontaining architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file. A first decoderfor the first instruction set and a second decoderfor the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitryfor supporting register renaming in conjunction with a physical register fileand an architectural register file

Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format

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Dripping Springs, TX, United States of America

Mark Carpenter Glass