International Business Machines Corporation

Mark C Johnson

Olivier Verscheure

Deepak Srinivas Turaga

Donald J Lang

Wei Fan

Adalberto Guillermo Yanes

Nagui Halim

Srinivasan Parthasarathy

Damon W Finney

Matthew Sean Grady

Forrest Lee Wade

Andrew Moy

Lih-Chung Kuo

Bitwoded Okbay

Sudha Sarma

Bradley D Pepper

Dean G Percy

Wen-Jei Ho

Joseph C Pranys

Chin-Huang Chen

The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.

Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure

Processing test results from a plurality of individual semiconductor testers by analyzing each test result at an adaptive test engine. A centralized system jointly analyzes all the test results from the plurality of individual semiconductor testers. The adaptive test engine or the centralized system identifies, based on the analysis of each test result or the joint analysis of all the test results, one or more of: a test environmental issue, a tester variability issue, a tester calibration issue, a product variability issue, and a manufacturing process variability issue. The adaptive test engine or the centralized system determines whether one or more of the plurality of individual semiconductor testers causes one or more of the identified issues or whether semiconductor products tested by the plurality of individual semiconductor testers causes one or more of the identified issues.

Integrated cross-tester analysis and real-time adaptive test

A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.

Integrated circuit test optimization using adaptive test pattern sampling algorithm

An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.

Apparatus, system, and method for managing errors in prefetched data

A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

Method and apparatus for parallel and pipelining transference of data

A dedicated debugging facility for tracing hardware and software faults in a distributed digital system. An event data capture circuit is integrated into each processing node in a distributed multinode system for capturing event data within each node under software control. The captured event data is stored in one of a plurality of variable-length trace data buffers in the node processor memory space for analysis or transfer. These dedicated trace data acquisition circuits provide continuously available trace data for the hardware and software functions within each node. Each variable-length trace data entry is stored in the trace data buffers according to a format of this invention that permits collection and assembly of trace data entries from throughout the distributed multinode system to debug local hardware or software and to debug internodal interconnection hardware and software.

Distributed trace data acquisition system

A memory controller reads data from a memory bank of synchronous RAM during a small and variable data valid window, by compensating for delays in receiving the data caused by memory loading, chip and card manufacturing process variations, and the like. The memory controller includes a system clock driver to supply the memory bank with a clock reference signal. A sampling clock provides an assortment of sampling clock signals duplicative of the system clock signal, with various delays. A command driver initiates Read operations in the memory bank by relaying Read command signals to the memory bank. In response to the level of memory loading, such as the number of memory modules present in the memory bank, a clock selector directs a selected one of the sampling clock signals to a delay module, which replicates any delay the system clock driver may have. If desired, an additional, user-selectable supplementary delay unit may be used to increase the delay provided by the delay module, thereby increasing or offsetting the delay of the selected sampling clock signal. The delay module provides a delayed clock signal to synchronize receipt of Read data signals from the memory bank at a clocked latch, enabling the latch to receive the Read data signals during the appropriate data valid window. Specifically, the latch is activated by receipt of Read command signals, which may be coordinated, for example, with the rising edge of the delayed clock signal. The latched Read data signals are then available for use by other logic circuitry.

Memory controller for reading data from synchronous RAM

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South Burlington, VT, United States of America

Mark C Johnson