Advanced Micro Devices Corporation

Mark C Gilmer

Mark I Gardner

Robert Paiz

Thomas E Spikes, Jr

H Jim Fulford

Daniel Kadosh

Derick J Wristers

Frederick N Hause

Jack C Lee

A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Method of making enhanced trench oxide with low temperature nitrogen integration

An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 &OHgr;-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600 to 900&deg; C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500 to 650&deg; C. A nitrogen bearing impurity distribution is then introduced into the conductive gate layer and the dielectric layer. The introduction of the nitrogen bearing impurity distribution is suitably accomplished by implanting a nitrogen bearing molecule such as N, N , NO, NF , N O, NH , or other nitrogen bearing molecule. Ideally, a peak concentration of the nitrogen bearing impurity distribution is in the range of approximately 1&times;10 to 1&times;10 atoms/cm and is located proximal to an interface of the conductive gate layer and the dielectric layer. Thereafter, an anneal may be performed, preferably in a rapid thermal process, at a temperature of approximately 900 to 1100&deg; C. for a duration of less than 5 minutes.

Nitrogenated gate structure for improved transistor performance and method for making same

A transistor is provided having a metal silicide gate spaced above a semiconductor substrate by a high-dielectric-constant ceramic gate dielectric. The entire gate conductor is preferably composed of a metal silicide. In an embodiment, the metal silicide is cobalt silicide and the ceramic gate dielectric is barium strontium titanate, lead lanthanum zirconate titanate barium zirconate titanate, cerium oxide, or tin oxide. In another embodiment, the ceramic gate dielectric has nitrogen atoms incorporated therein. The transistor may also include dielectric spacers adjacent opposed sidewall surfaces of the gate conductor, lightly doped drain regions arranged underneath the spacers, and source and drain regions arranged adjacent the lightly doped drain regions.

Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant

The present disclosure relates to a chemical vapor deposition system including a chemical vapor deposition chamber, and a circlet wafer positioned within the chemical vapor deposition chamber. The circlet wafer is mounted on a rotatable member that at least partially extends through an opening of the wafer. A drive mechanism is used to rotate the rotatable member and the circlet wafer. The system also includes a gas injector for injecting reactive gases toward the circlet wafer. The present disclosure also relates to a chemical vapor deposition system including a chemical vapor deposition chamber, a wafer positioned within the chemical vapor deposition chamber, and a gas injector for injecting first and second reactive gases toward the wafer. The gas injector includes a mixing region for mixing the first and second reactive gases before the first and second reactive gases are discharged from the gas injector.

Chemical vapor deposition systems and methods for depositing films on semiconductor wafers

The present invention generally provides a semiconductor device and fabrication process in which gate electrode formation is integrated with the formation of isolation regions. Consistent with one embodiment of the invention, the semiconductor device is formed by forming at least two adjacent gate electrode stacks of the substrate. A layer of dielectric material is formed over regions of the substrate between the two adjacent gate electrode stacks and portions of the dielectric material layer are selectively removed to leave an isolation block of the dielectric material between the two adjacent gate electrode stacks. The gate electrode stacks may, for example, have a thickness ranging from about 2,500 to 6,000 &angst;. In accordance with one aspect of the invention, active regions are formed in the substrate between the isolation block and at least one of the gate electrode stacks.

Method of forming a semiconductor device having integrated electrode and isolation region formation

A transistor and a method of making the same are provided. The transistor includes a substrate and a gate dielectric layer positioned on the substrate that has first and second sidewall spacers. A gate electrode is positioned on the gate dielectric layer between the first and second sidewall spacers. A semiconductor layer is positioned on the substrate and adjacent the gate dielectric layer. First and second source/drain regions are provided wherein each of the first and second source/drain regions has a first portion positioned in the semiconductor layer and a second portion positioned in the substrate. Processing of the gate dielectric layer and the sidewall spacers is integrated.

Method of making elevated source/drain using poly underlayer

A semiconductor device having a reduced polysilicon gate electrode width and a process for manufacturing such a device is provided. Consistent with the present invention a semiconductor device is formed by forming an insulating film selective to oxide etchant over a substrate. At least one polysilicon block is formed over the insulating film. The polysilicon block is oxidized to grow an oxide layer on exposed surfaces of the polysilicon block and thereby reduce the width of the polysilicon block. The oxide layer is then removed to form a gate electrode with the remaining portion of the polysilicon block. In this manner, gate electrodes having widths smaller than the resolution of current etching techniques can be formed. In accordance with one aspect of the invention, the polysilicon gate electrode has a width less than about 0.15 microns. In accordance with another aspect, the insulating layer selective to oxide etchant is formed from a high permittivity material, such as a barium strontium titanate oxide.

Semiconductor device having reduced polysilicon gate electrode width and method of manufacture thereof

In insulated-gate, field effect transistor (IGFET) devices fabricated in integrated circuits, the scaling down of the dimensions of the devices has resulted in structures with dimensions are so small that reproducibility of parameters can become problematic. Specifically, the gate dielectric, typically silicon nitride, silicon oxide or silicon nitride, of a gate structure is nearing the point where the required thickness of the gate dielectric to provide the selected electric field in the channel region is implemented with a few to several atomic layers. In order to improve parameter reproducibility, a dielectric material, such TaO,or a ferroelectric material, is used as a gate dielectric. TaO,and the ferroelectric materials have a dielectric constant an order of magnitude higher than the material typically used in the past. Using these materials, the gate dielectric can be proportionately thicker, thereby improving the parameter reproducibility.

Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices

In an integrated circuit, a pair of IGFET devices can be formed with reduced dimensions without requiring the use of higher resolution optical masks. A gate electrode is formed with a layer of silicon nitride and a photoresist layer formed thereon. The dimensions of the photoresist layer are reduced by a trim etch and the dimension of the nitride layer reduced by a nitride etch. After removing the photoresist layer, a silicon oxide layer is grown over the exposed gate electrode and substrate. The nitride layer is removed leaving a pattern in the silicon oxide layer. An anisotropic etch guided by the pattern in the silicon oxide layer divides the gate electrode into two portions with an aperture therebetween. By proper doping, a IGFET structure can be formed that has two IGFET devices having a shared source/drain region and occupying the same area on the surface of the substrate as a single IGFET device previously occupied.

High density mosfet fabrication method with integrated device scaling

A semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface followed by an in situ deposition of polysilicon are used to create a thin oxide MOS structure. Preliminarily, the upper surface of a semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the substrate. A first polysilicon layer is then in situ deposited on the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O,. The ambient temperature of the first oxidation chamber is preferably maintained at a temperature less than approximately 300&deg; C. during the formation of the gate dielectric. The first polysilicon layer, in the preferred embodiment, is deposited in situ such that the semiconductor substrate remains within the first oxidation chamber during the deposition of the first polysilicon layer. The oxidation of an upper portion of the first polysilicon layer is preferably accomplished in a nitrogen bearing ambient so that nitrogen is introduced into the first polysilicon layer to inhibit the penetration of mobile impurities across the gate dielectric into the channel region of the transistor and enhance the device properties.

Method of forming ultra-thin oxides with low temperature oxidation

The present invention is directed to a semiconductor device having an improved structure for isolating transistors formed on a semiconductor substrate, and a method for making same. The device is comprised of a semiconductor device having first and second recesses formed in the substrate of the device. The inventive method disclosed herein comprises forming first and second recesses in the substrate of the device. The first width of the first recess is formed such that it is greater than the second width of the second recess, and the second depth of the second recess is formed such that it is greater than the first depth of the first recess.

Advanced isolation structure for high density semiconductor devices

A transistor and a method of making the same are provided. The method includes the steps of forming a gate dielectric stack on the substrate that has a gate dielectric layer and forming first and second sidewall spacers adjacent the gate dielectric stack. A first portion of the gate dielectric stack is removed while a second portion thereof is left in place. First and second source/drain regions are formed in the substrate, and a conductor layer is formed over the first and second source/drain regions and on the second portion of the gate dielectric stack. The gate dielectric may be composed of a high dielectric constant material with a thin equivalent thickness of oxide. The method enables integrated processing of the gate electrode and source/drain metallization.

Method of making high performance MOSFET with polished gate and source/drain feature

An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination. The transistors and other circuit elements formed in the substrate may be interconnected to form an integrated circuit.

Integrated circuit having transistors that include insulative punchthrough regions and method of formation

An integrated circuit fabrication process is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, sidewall spacers are formed laterally adjacent opposed sidewall surfaces of the gate electrode. An interlevel dielectric is then formed above the semiconductor substrate and selectively removed from above active regions of the semiconductor substrate to form an opening. Source and drain implant areas are formed self-aligned with the opposed sidewall spacers. A metal silicide layer may be formed across upper surfaces of the gate conductor and source and drain areas, a second interlevel dielectric deposited in the opening, and contacts formed through the second interlevel dielectric to the metal silicide. In an alternative embodiment, the gate dielectric may be formed sufficiently thick such that sidewall spacers are unnecessary to prevent silicide bridging between the gate conductor and the junction regions. In another alternative embodiment, the lightly doped drain implant areas may be formed self-aligned to the gate electrode prior to spacer formation.

Source/drain and lightly doped drain formation at post interlevel dielectric isolation with high-K gate electrode design

The present invention is directed to a novel semiconductor device and a method for making same. As disclosed herein, a gate dielectric comprised of epitaxial metal oxide is positioned above a semiconducting substrate. A gate conductor comprised of an epitaxial conductive material is positioned above the gate dielectric. The method comprises forming a layer of an epitaxial metal oxide above a semiconducting substrate, forming a layer of epitaxial conductive material above the layer of epitaxial metal oxide, and forming a source/drain region.

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Austin, TX, United States of America

Mark C Gilmer