Texas Instruments Corporation

Mark C Carlos

William R Manning

Stanley J Nacewicz

Lawrence P Kleven

A phase sequence protection circuit is shown in which first and second resistors (R1, R2) and a first capacitor (C1) all having equivalent impedance are connected in a Y configuration and coupled to power source leads (A, C, B) of a three phase power supply, resistor R1 being coupled to phase A, capacitor C1 to phase B and resistor R2 to phase C. A comparator network (12) is connected in line with the first resistor (R1) and, in one embodiment will cause a solid state switch (Q1) to conduct when the phases are out of sequence. In a second embodiment a buffer portion (COMP2) is provided to add switching hysteresis which also reverses the switching logic causing the solid state switch (Q1) to conduct when the phases are in sequence. In another embodiment the comparator network (12') is provided with the buffer portion (COMP2) for switching hysteresis and arranged to cause the solid state switch (Q1) to conduct when the phases are out of sequence. An opto-isolator (14) interfaces with the comparator network (12, 12', 12') to provide isolation. The signal from the opto-isolator in comparator network (12') controls the energization of a second solid state switch (Q2) and a relay coil (K1) used to energize a load.

Phase sequence wiring protection apparatus

A three pole relay is shown which operates in response to the flow of normal operating current across fluorescent lamps to energize a coil which actuates a relay to open switches disposed in all of the filament lines associated with the lamp to shut off filament current while maintaining current flow across the lamps themselves.

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North Providence, RI, United States of America

Mark C Carlos