Advanced Micro Devices Corporation

Mark Buckler

Srilatha Manne

Wayne Burleson

Sudha Thiruvengadam

Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous system using an array of digital frequency measurement circuits that provide overlapping frequency and detection interval measurements within single counter periods required for a single frequency measurement circuit to complete a frequency measurement. Embodiments may be used in a predictive synchronizer to provide low latency, continuous frequency measurements for system-on-chip (SOC) devices that employ frequency drift or ramping to reduce power consumption and overheating conditions.

Continuous frequency measurement for predictive periodic synchronization

A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Methods and systems of synchronizer selection

Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.

Predictive periodic synchronization using phase-locked loop digital ratio updates

An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.

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Acton, MA, United States of America

Mark Buckler