Texas Instruments Corporation

Mark Bryan Hamlyn

Charles Parkhurst

Hector Torres

A circuit includes a fuse cell with a current mirror. The first leg of the current minor includes first and second N-type transistors coupled in series between the upper and lower rails and the second leg includes third and fourth N-type transistors coupled in series between the upper and lower rails. The size of the first N-type transistor is (Y&#xb7;A), the second N-type transistor is (X&#xb7;A), the third N-type transistor is (X&#xb7;A) and the fourth N-type transistor is (Y&#xb7;A) where X and Y are integers and Aand Aare the sizes of respective reference transistors. A fuse has a first terminal coupled between the first and second N-type transistors and a second terminal coupled between the third and fourth N-type transistors; a first control node on the second leg of the current minor is coupled to control the voltage at an output node of the fuse cell.

Zero bias fuse cell

A fault tolerant voltage regulator may include a plurality of operational transconductance amplifiers. The plurality of operational transconductance amplifiers may be configured according to a unity-gain configuration. The plurality of operational transconductance amplifiers may be configured to couple in parallel to a load. The plurality of operational transconductance amplifiers may be configured to load share a load current associated with the load approximately equally among the plurality of operational transconductance amplifiers.

Fault tolerant voltage regulator

Apparatus and methods operate to disable a dynamically biased apparatus and a dynamic bias current source providing dynamic bias current to the apparatus at the beginning of a static bias startup period shortly after power-on. The dynamically biased apparatus is then gradually enabled in a static bias mode of operation during the static bias startup period. Following the end of the static bias startup period, operation of the dynamically biased apparatus in a dynamic transconductance mode is gradually enabled during a dynamic bias startup period. Such startup sequence operates to prevent damaging in-rush currents in a system employing the dynamically biased apparatus in a feedback control loop.

Dynamic bias soft start control apparatus and methods

Systems and methods for radiation-tolerant overcurrent detection are disclosed. In some embodiments, an integrated circuit may include a plurality of overcurrent detectors, each of the plurality of overcurrent detectors configured to detect a candidate overcurrent event. The integrated circuit may also include a voting circuit coupled to the overcurrent detectors, the voting circuit configured to indicate an overcurrent in response to receiving a selected number of candidate overcurrent events from the overcurrent detectors. At least one of the overcurrent detectors may be subject to detecting the candidate overcurrent in error, at least in part, due to exposure to ionizing radiation.

Radiation-tolerant overcurrent detection

Apparatus and methods disclosed herein operate to receive a differential input signal at a first-stage pair of transconductance devices. The differential signal is amplified by a second-order factor at a positive-side or a negative-side first-stage transconductance device, depending upon the polarity of the differential input signal, to create a second-order signal at the output of the appropriate first-stage device. The second-order output signal is then amplified by another second-order factor at a corresponding second-stage transconductance device. A resulting fourth-order signal is made available at an output node as a quartic-response current source. The quartic-response current source may be utilized as a dynamic bias source in conjunction with a linear amplifier to provide a high slew rate amplifier.

Fourth-order electrical current source apparatus, systems and methods

A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation.

Growing community of inventors

McKinney, TX, United States of America

Mark Bryan Hamlyn