Xilinx, Inc.

Mark Brian Roberts

Scott K Roberts

James Karp

Richard P Burnley

Mohammed Fakhruddin

Min-Hsing Chen

Robert E Eccles

Kuok-Khian Lo

An embodiment of the invention involves: providing a database that includes layout information representing a layout within an integrated circuit of an electrical circuit; identifying from the information in the database each conductive path of a selected type in the electrical circuit; extracting layout information from the database for each conductive path of the selected type; and calculating an electrical parameter for each conductive path of the selected type, as a function of the layout information obtained for that conductive path during the extracting. In addition, in a different configuration of the embodiment, a report can be generated containing information based on the electrical parameter calculated during the calculating for at least one of the conductive paths of the selected type.

Method and apparatus for evaluating paths in an integrated circuit design

Method, apparatus, and computer readable medium for performing electrical rule checks (ERCs) on a circuit design are described. In one example, a hierarchy of cell instances is created from a schematic database for the circuit design. The hierarchy is traversed to produce master nets. Each of the master nets is associated with shorted nets in the circuit design. The hierarchy is traversed to produce ERC nets. Each of the ERC nets is associated with effectively shorted nets in the circuit design. At least one pair of the effectively shorted nets is effectively shorted across a transistor. At least one ERC is performed on the circuit design using the master nets and the ERC nets.

Method and apparatus for performing electrical rule checks on a circuit design

A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.

Method and system for generating multiple implementation views of an IC design

A method and system for generating implementation files from a high level specification are described. In one example, a method for creating a package file for an integrated circuit is described. First, a grid is formed having a plurality of blocks. A height and a width are then determined for each block. At least one bump is placed on a block and a corresponding package pin is assigned to the at least one bump. Finally, the package file is output.

Method and system for generating implementation files from a high level specification

An aspect of the invention relates to a method, apparatus, and computer-readable medium for processing schematic data for an integrated circuit having a boundary scan architecture. A path through cells of the schematic data to generate a hierarchy of cells associated with a boundary scan chain. Each ignore cell in the hierarchy is pruned. Each short cell in the hierarchy is replaced with a direct connection. A shadow net is added to each net of the hierarchy. Each of the cells in the hierarchy is flattened in a bottom-up fashion.

Method and apparatus for generating a boundary scan description and model

Method and apparatus are described for providing a rule file. More particularly, a design rule document is converted to a table file of design rules and associated design rule values, where design rules follow a naming convention to maintain uniqueness among them. A parameterized design rule check (PDRC) file is obtained. Such a PDRC file calls out design rule names instead of design rule values. A computer program is used to exchange design rule values associated with design rule names in the table file for the design rule names called out in the PDRC file to provide a design rule check (DRC) file. This method and apparatus also apply to any technology file containing parameterized rules.

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Auburn, CA, United States of America

Mark Brian Roberts