Micron Technology Incorporated

Mark Bossler

William A Polinsky

Jaspreet Singh Gandhi

Christopher J Gambee

Randall S Parker

Thomas S Kari

Anilkumar Chandolu

Sameer S Vadhavkar

Wayne H Huang

Giorgio Mariottini

Chris L Inman

Dirk J Sundt

Gabriel G Videla

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Collars for under-bump metal structures and associated systems and methods

A method for selectively removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SFwithout forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Semiconductor structures comprising at least one through-substrate via filled with conductive materials

A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SFwithout forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Methods of selectively removing a substrate material

A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is a plasma sputter etch to form a facet profile. The first stage etch is terminated prior to reaching the target depth for the etching process. The second stage etch is a reactive ion etch which directionally follows the facet profile to reach the target depth.

Modified facet etch to prevent blown gate oxide and increase etch chamber life

A modified facet is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is a plasma sputter etch to form a facet profile. The first stage etch is terminated prior to reaching the target depth for the etching process. The second stage etch is a reactive ion etch which directionally follows the facet profile to reach the target depth.

Structure and method for filling an opening in a semiconductor structure that is less susceptible to the formation of voids. A first layer of a first material is formed over the layer in which the opening is to be formed, and a faceted opening is formed in the first layer. The opening in the underlying layer is subsequently formed, and the material that is to fill the opening is deposited over the faceted opening and into the opening of the underlying layer.

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Meridian, ID, United States of America

Mark Bossler