Netlogic Microsystems, Inc

Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Mark Birman

Sandeep Khanna

Maheshwaran Srinivasan

Varadarajan Srinivasan

Sachin Joshi

Srinivasan Venkatachary

Alexei Starovoitov

Ajay Srikrishna

Cristian Estan

Pankaj Gupta

Ashish Goel

Greg Watson

Andrew Rosman

Bhaswar Mitra

Laxminarasimha Rao Kesiraju

Prashanth Narayanaswamy

A system including memory, a lookup circuit and an address circuit. The memory can store a plurality of tables. Each table can have a plurality of entries and each entry can have an entry index. The lookup circuit can be coupled with the memory. The lookup circuit can provide the plurality of entry indexes of the plurality of tables to the address circuit. The address circuit can include a first circuit, a second circuit, and third circuit. The first circuit can include a plurality of entry scramblers. The second circuit can include a plurality of translators, and the third circuit can include a plurality of row scramblers.

Systems and methods for address scrambling

In some aspects, the disclosure is directed to methods and systems for providing an architecture for building high performance silicon components that support a rich set of networking and security features. In many implementations, the architecture splits network and security functions into two functional and logical blocks (which may physically be on the same die or integrated circuit in some implementations, or may be split on separate integrated circuits). The network functions may be executed via an integrated network interface card and accelerator subsystem with a high throughput execution pipeline. Security functions may be executed asynchronously from the network processing functions, in many implementations.

High performance architecture for converged security systems and appliances

Methods, systems, and computer readable storage medium embodiments for configuring a lookup table, such as an access control list (ACL) for a network device are disclosed. Aspects of these embodiments include storing a plurality of data entries in a memory, each of the stored plurality of data entries including a header part and a body part, and encoding each of a plurality of bit-sequences in the header part of a stored data entry from the plurality of data entries to indicate a bit comparing action associated with a respective bit sequence in the body part of the stored data entry. Other embodiments include searching a lookup table in a network device.

Organizing data in a hybrid memory for search operations

A content search system for determining whether an input string matches one or more rules includes a parser, a rules database, and a search engine. The parser, which has an input to receive the input string, is to extract one or more selected portions of the input string to form a filtered input string, and is to generate a rule select signal in response to the selected portions of the input string. The rules database stores a plurality of sets of rules. The search engine is to compare the filtered input string with a selected set of rules selected in response to the rule select signal.

Targeted search system with de-obfuscating functionality

A search system for detecting whether one or more overlapping sequences of input characters match a regular expression including a prefix string preceding an intermediate expression having a quantified number m of characters belonging to a specified character class is disclosed. The search system includes a CAM array for storing the regular expression, a shift register for counting sequences of input characters that match the character class, and a control circuit that enables the shift register in response to a prefix match and increments the shift register in response to character class matches.

Content addressable memory having selectively interconnected shift register circuits

A data stream search system can include a plurality of search data inputs logically divided into at least M+N sets. The sets have a logical order with respect to one another, each set providing more than one bit value. A key application circuit can comprise a plurality of data paths that each couple a different group of at least M data input sets to a corresponding content addressable memory (CAM) section. Each different group of at least M data input sets can be contiguous with respect to the logical order, and shifted in bit order from one another by at least two bits.

Pattern matching system and method for data streams, including deep packet inspection

A content search system includes CAM device, a compiler, and an image loader. The CAM device, which includes a plurality of rows of CAM cells and a number of counter circuits selectively interconnected by a programmable interconnect structure (PRS), performs regular expression search operations. The compiler selectively converts the regular expression into a number of various bit groups, and the image loader loads corresponding bit groups into the CAM cells, into a number of memory elements that control configuration of the PRS, and into the counter circuits.

Compiling regular expressions for programmable content addressable memory devices

An apparatus and method of programming a search engine to implement regular expression search operations are disclosed that selectively transform a source regular expression into an equivalent reformulated regular expression in response to a determination of the architectural characteristics of the search engine. In this manner, the regular expression can be reformulated to optimize the configuration and available resources of the associated search engine.

Reformulating regular expressions into architecture-dependent bit groups

A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Power reduction in a content addressable memory having programmable interconnect structure

A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Content addressable memory having selectively interconnected rows of counter circuits

A content addressable memory device () and method can have CAM blocks (-to-) organized in block sections (-to-). In an overlay mode of operation, an overlay engine () can access an algorithmic search (SPEAR) CAM (-and-) to generate overlay data set search keys (keyFIB&#x3c;&#x3e; and &#x3c;&#x3e;). Multiple data sets (e.g., FIB, FIB, ACL) can be accommodated on the same CAM device by search key multiplexers (-to-) that selectively apply any of a number of data set search keys (keyACL&#x3c;&#x3e;, keyFIB&#x3c;&#x3e; and keyFIB&#x3c;&#x3e;).

Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device

Content addresable memory having selectively interconnected counter circuits

Content addresable memory having programmable interconnect structure

A content addressable memory (CAM) device includes a plurality of independently configurable CAM groups, each CAM group including a number of CAM rows and a programmable combinational logic circuit. Each CAM row includes a plurality of CAM cells coupled to a match line that generates a row match signal during a compare operation between a search key and data stored in the CAM row. The programmable combinational logic circuit logically combines the row match signals to generate a corresponding group match signal according to a respective one of a plurality of selectable logical operations selected by a corresponding function select signal.

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Los Altos, CA, United States of America

Mark Birman