Texas Instruments Corporation

Mark Benjamin Welty

Zhao Fang

Eddie W Yu

Vrashank Gurudatta Shukla

Emmanuel Osei Boakye

Lifang Lou

An electronic device includes a first-conductivity-type substrate and a second-conductivity-type epitaxial layer having a first dopant concentration. A first substrate region includes a second-conductivity-type buried layer and is enclosed by a first deep isolation structure. Within the first substrate region are a first doped region having the second conductivity type and a dopant concentration greater than the first dopant concentration and a second doped region having the first conductivity type. A second substrate region includes a first-conductivity-type buried layer and is enclosed by a second deep isolation structure. Within the second substrate region is a third doped region having the second conductivity type and a dopant concentration greater than the first dopant concentration.

Monolithic multi-channel diode array

A bidirectional flat clamp device includes a first device node and a second device node. The bidirectional flat clamp device also includes a first switch and a second switch coupled in series between the first and second device nodes. The bidirectional flat clamp device also includes at least one switch driver coupled to the first and second switches. The bidirectional flat clamp device also includes a first current path between the first and second device nodes, the first current path having a first diode, a voltage sensor circuit, and a second diode. The bidirectional flat clamp device also includes a second current path between the first and second device nodes, the second current path having a third diode, the voltage sensor circuit, and a fourth diode.

Bidirectional flat clamp device with shared voltage sensor circuit

A surge protection device for providing bidirectional detections of one or more surge events. The device has low dynamic resistance during a surge protection mode, and it conducts ultra-low leakage current outside of the surge protection mode. In one implementation, the device includes first and second power transistors, a sensing circuit, and a driver circuit. The first power transistor includes a first source terminal that is coupled to the substrate, and the second power transistor includes a second source terminal that is coupled to the substrate. The sensing circuit is configured to detect a voltage of the first pin relative to the second pin and generate a sense signal when the voltage exceeds a threshold. The driver circuit is configured to generate a driver signal based on the sense signal and output the driver signal to at least one of the first or second gate terminal.

Bidirectional precision surge clamp with near-zero dynamic resistance and ultra-low leakage current

An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD event detector. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.

ESD positive and negative detection and capture, and logging circuitry

An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD detection circuitry. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.

Logging ESD events

The accelerator output stage circuit includes: a high side output device coupled to an output node; a low side output device coupled to the output node; a first logic gate coupled to a control node of the first high side output device; a second logic gate coupled to a control node of the second high side output device; a high side one-shot device having an output coupled to a first input of the first logic gate; a low side one-shot device having an output coupled to a first input of the second logic gate; and a feedback device coupled between the output node and a second input of the first logic gate, and between the output node and a second input of the second logic gate, and between the output node and the input to the high side resistor bypass device, and between the output node and the input to the low side one-shot resistor bypass device.

Accelerator output stage that adjusts drive duration to loading

In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bi-directional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of operation. The voltage translator includes edge-rate accelerators to detect signal transitions and includes configurable resistors to provide a direct current (DC) drive current and a DC bias to hold desired voltage levels. The voltage translator is operable in the open-drain mode to detect a presence of an electronic device, and is operable in the push-pull mode upon the detection of the electronic device.

Semi-buffered auto-direction-sensing voltage translator

A pass transistor signal level translator between a first voltage level and a higher second voltage level having a bias circuit for the pass transistor including a first switching circuit coupled to the first voltage level for providing a bias voltage that is less than the first voltage level. A second switching circuit is coupled to the second voltage level for providing a pulse at substantially the second voltage to the bias voltage. A voltage clamping circuit is coupled between the bias voltage and a reference voltage.

Biasing circuit for pass transistor for voltage level translator circuit

In a method and apparatus for rapidly recovering an improved amplifier from an overload condition, a cascode amplifier (CASA) having a pair of inputs and an output is coupled to an overload recovery circuit (ORC). The pair of inputs is coupled to receive a differential input signal. A deviation in the differential input signal that is greater than a threshold causes a deviation in a current provided to at least one transistor included in the CASA. The deviation in the current causes the CASA to operate in an overload condition (OC). The ORC includes a makeup current circuit operable to generate an overload current in response to the OC and a controller operable to control a voltage at the output during the OC. The controller coupled to the makeup current circuit provides the overload current to the CASA to enable the rapid recovery from the OC.

Overload recovery circuit for folded cascode amplifiers

A transition detect circuit includes: a first input port referenced to a first supply voltage node and a second input port referenced to a second supply voltage node. The circuit simultaneously monitors both ports for transitions, and once a transition occurs, directly generates the translated control signals at its output. Once a transition occurs at the inputs, the translated control signal is generated at the output within at most two gate delays. The circuit has very low quiescent current.

Circuit for detecting transitions on either of two signal lines referenced at different power supply levels

A blocking circuit technique achieves very low Ioff and Ioz leakage in low power digital logic devices that incorporate Ioff and overvoltage tolerance. The blocking circuit employs a diode-connected P-channel device in parallel with a PN diode. The diode-connected P-channel device provides enough forward leakage in the subthreshold region to keep Ioz through the upper output driver to a very low level (0.2 uA typical). Further, both the diode-connected P-channel device and the PN diode together provide enough reverse blocking capability to keep Ioff to a very low level (0.2 uA typical).

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McKinney, TX, United States of America

Mark Benjamin Welty