Discovision Associates

Mark Barnes

Anthony Mark Jones

William P Robbins

Anthony Peter Claydon

Adrian Philip Wise

Martin William Sotheran

Helen Rosemary Finch

Nicholas Birch

David Andrew Barnes

Andrew Peter Kuligowski

Colin Smith

Kevin D Dewar

Donald William Patterson

Richard J Gammack

Charles Dunlop MacFarlane

Anthony Peter J Claydon

Kevin Douglas Dewar

Donald W Walker Patterson

A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

Memory interface for reading/writing data from/to a memory

A CMOS Reed-Solomon decoding circuit calculates syndromes, executes a Berlekamp algorithm, performs a Chien Search, and corrects a delayed version of the received data according to a calculated magnitude of error. The circuit is optimized in terms of chip territory and circuit complexity. Signals are provided to indicate uncorrectable packet errors and other transmission errors.

Signal processing apparatus and method

An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Token-based adaptive video processing arrangement

A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to another rate, while still maintaining a desired rate. In the invention, the write control and read control both have state indicators for communicating which buffer they are using and whether the controls are waiting for access or are, in fact, accessing that buffer.

Technique for implementing a swing buffer in a memory array

Video decompression

Arrangement for processing packetized data

An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.

Growing community of inventors

Chippenham, United Kingdom

Mark Barnes