Cadence Design Systems, Inc.

Mark Baker

Donald John O'Riordan

Keith Dennison

Bogdan George Arsintescu

Ian Campbell Dennison

A system, method, and computer program product for automatically providing circuit designers with verification information for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to enter verification IP while simultaneously viewing the design IP in a schematic and/or layout editor window. Embodiments maintain the verification IP in a cellview similar to the separate cellviews used for schematic and layout data. Verification IP may be selectively translated into data that is directly exportable to and usable by particular analog and mixed-signal simulators. Embodiments direct design IP and verification IP to a simulator that dynamically stitches both together during circuit verification, and tangibly outputs verification results.

System and method for analog verification IP authoring and storage

A computer-implemented method of identifying sub-circuits in circuit designs includes: receiving a selection of a sub-circuit; specifying a match expression for the sub-circuit, where the match expression characterizes matching properties of components of the sub-circuit; modifying the match expression to change the matching properties of components of the sub-circuit; and producing an information structure in a computer readable medium, where the information structure associates a graph representing a topology of the selected sub-circuit with the modified match expression. Subsequently, the information structure corresponding to the selected sub-circuit can be identified in a given circuit design.

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Kinross, United Kingdom

Mark Baker