Intel Corporation

Mark B Trobough

Christopher S Baldwin

Leonard O Turner

Ashok N Kabadi

Ron Flamm

Henning Braunisch

Daoqiang Lu

David W Grawrock

Michael W Leddige

Bruce Querbach

Tieyu Zheng

Keshavan K Tiruvallur

Chinna B Prudvi

Gerald A Budelman

Hermann Gartler

Vui Yong Liew

Mohiuddin M Mazumder

Samie B Samaan

Keith A Drescher

Mukesh Kataria

Richard J Glass

Jay Joseph Nejedlo

Lyle E Cool

Russell J Wunderlich

James J Grealish

Ven R Holalkere

Brian Meyer

Alok Tripathi

Abhijit Davare

Priyadarsan Patra

Ridvan A Sahan

Bram Leader

William Penner

Rahima K Mohammed

Michael J Baker

Wee Hoo Cheah

Arun R Ramadorai

Yuen Tat Lee

Kapila B Udawatta

John L Baudrexl

Christian E Iovin

Kip C Killpack

Loren James McConnell

Kyle Markley

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

Travis K Goff

David C Florey

Evan J Halprin

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Pascal C Meier

Timothy S Storey

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates

Disclosed is an interposer for accessing one or more signals from an Integrated Circuit (IC) package. The interposer is disposed between the IC package and a socket body. The interposer comprises a plurality of clearance holes and at least one connecting element. The plurality of clearance holes allows an array of contacts on a first surface of the socket body to pass through the interposer and make electrical contact with a first set of contacts of a plurality of contacts of the IC package. The at least one connecting element is configured to make electrical contact with a second set of contacts of the plurality of contacts of the IC package. The electrical contact between the at least one connecting element and the second set of contacts of the plurality of contacts of the IC package provides access to the one or more signals from the IC package.

Non-intrusive interposer for accessing integrated circuit package signals

An apparatus includes a printed circuit board (PCB) and a first flexible conductive cable ('flex cable') secured to the PCB. The apparatus also includes a daughter card having an end adjacent to the PCB and a second flex cable secured to the daughter card. The apparatus further includes a connector which provides an electrically conductive connection between the first flex cable and the second flex cable. The connector is positioned to sandwich a portion of the first flex cable between the connector and the PCB.

Technique for blind-mating daughtercard to mainboard

A coupler is passively aligned over a substrate, wherein the coupler is laterally aligned to an optoelectronic (OE) device coupled to the substrate. The coupler is placed on the substrate, wherein the coupler is vertically aligned to the OE device. The coupler is fixed to the substrate.

Optical interconnect with passive optical alignment

In some embodiments, a socket with integral, retractable socket contact protector is presented. In this regard, a contact protector is introduced to protect contacts, and to provide openings through which the contacts can emerge to couple with lands. Other embodiments are also disclosed and claimed.

Socket with integral, retractable socket contact protector

Circuit board and system with multi-portion sockets, and signal methods practiced thereon are described herein.

Circuit board and system with a multi-portion socket

An assembly including a processor socket having a cut region. The assemble further including a probe board having a repeater positioned in alignment with the cut region. The repeater is to receive at least a first signal. The repeater is to tap the first signal. The tapped first signal is to be transmitted to a first device. The repeater is also to reinject the first signal, and the reinjected first signal to be transmitted to a processor.

Method and apparatus to probe bus signals using repeaters

A multi-portion socket, related components, and systems having such socket/components are described herein.

Multi-portion socket and related apparatuses

A method for producing a heat sink includes extruding a first material in a second material, and cut into a billet. The second material is removed from the billet to produce a base and a plurality of fins. The second material is removed from the billet by placing the billet into a chemical bath. The heat sink is rinsed to remove chemical residue from the heat sink. Mounting holes are stamped into the base, and a mounting surface is ground on the heat sink. Another method for producing a heat sink includes ramming fins into a base. The base is heated prior to the entry of the fins. The base is also provided with dimples to accept entry of the fins.

Apparatus for producing high efficiency heat sinks

Method and apparatus for producing high efficiency heat sinks

A socket includes a mechanism to gain electrical access to integrated circuit package pins in an end-user system. A pin grid array (PGA) socket includes signal traces that lead to a connector accessible by test equipment. In one embodiment, the PGA socket is a zero insertion force (ZIF) socket, and in other embodiments, the PGA socket is a low insertion force (LIF) socket. In other embodiments, multiple PGA sockets are interconnected.

Pin grid array socket

Growing community of inventors

Olympia, WA, United States of America

Mark B Trobough