Intel Corporation

Mellanox Technologies, Ltd.

Nvidia Corporation

Tilera Corporation

Mark B Rosenbluth

Gilbert M Wolrich

Debra Bernstein

Ilan Pardo

Debendra Das Sharma

David J Harriman

Robert G Blankenship

Mahesh U Wagh

Jasmin Ajanovic

Scott Dion Rodgers

Anil Vasudevan

Prashant Sethi

Sridhar Muthrasanallur

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Eliezer Weissmann

Ohad Falik

Mason B Cabot

Matthew James Adiletta

Sridhar Lakshmanamurthy

Frank T Hady

Abraham Mendelson

John Beck

Sanjeev Jain

Hugh M Wilkinson, Iii

Rui Xu

Michael Cotsford

Donald F Hooper

Myles Wilde

Avi Mendelson

Diane Orf

Bijoy Bose

Carl Ramey

Lawrence B Huston

Irwin J Vaz

Avi (Abraham) Mendelson

Shreya Tekade

Prashant R Chandra

Idan Burstein

Hugh Wilkinson

Christopher J Jackson

Jose Niell

Michael F Fallon

Rohit Natarajan

Chen-Chi Kuo

Yim Pun

Raymond Ng

Richard Guerin

James D Guilford

Anant Agarwal

Pete D Vogt

Matthew Mattina

David M Wentzlaff

Charles E Narad

Ian Rudolf Bratt

Bruce Edwards

Hillel Chapman

Yamin Friedman

Suri B Medapati

Aaron R Kunze

Alok Kumar Mathur

Richard Schooler

Christopher D Metcalf

Oded Lempel

Liewei Bao

Chyi-Chang Miao

Patrick Robert Griffin

Anurag Chaudhary

Sameer Nanavati

Kenneth M Steele

Shane Bell

David Romano

David Lawrence Tennenhouse

John A Amann

Robert J Kushlis

Xiao-Feng Li

Dz-ching (Roy) Ju

Mathew Hostetter

Eric Walker

Benjamin Cahill

Dennis Rivard

Richard Conlin

Tsofia Eshel

Thomas L Dmukauskas

Ben Harrison

Kevin Joyce

Christine Deignan

Matt Orsini

Ohad Fallk

Ellezer Weissmann

Avi (Arraham) Mendelson

Jeen-Xuan Miin

Edwin O'Yang

John Sweeney

Ariel Szapiro

Mayank Baunthiyal

David Woods

A system includes a functional unit having a processor and address management circuitry. The address management circuitry is to receive a request from the processor, where the request is associated with a boot process initialized at the processor. The address management circuitry is to determine a bit stored at the address management circuitry has a first value indicating to associate the request with a first node identifier associated with a memory region storing data associated with the boot process instead of a second node identifier associated with nodes storing physical locations associated with a memory address of the request. The address management circuitry can further transmit the request with the first node identifier to logic at a first node coupled to the memory region responsive to determining the bit has the first value.

Boot initialization without home node involvement

Various embodiments include techniques for storing data in a repurposed cache memory in a computing system. The disclosed techniques include a system level cache controller that processes a memory operation for a processing unit. The controller and the processing unit communicate over a network-on-chip. To process the memory operation, the controller selects a repurposed cache memory from a pool of active cache memories associated with processing units that are inoperable and/or are in a low-power state. To select the repurposed cache memory, the controller generates a candidate vector that identifies the position of the requesting processing unit relative to the controller. The candidate vector enables the controller in selecting a repurposed cache memory that is, for example, on the shortest path between the processing unit and the controller. These techniques result in a lower latency, and improved memory performance, relative to prior conventional techniques.

Cache locality when using repurposed cache memory

A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.

Virtual wire protocol for transmitting side band channels

A system including an array of functional units connected via a two-dimensional mesh network is described. A first functional unit in the array of function units includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including generating a node identifier identifying a second functional unit in the array of functional units, and transmitting, over the two-dimensional mesh network, the node identifier identifying the second functional unit in the array of functional units. The node identifier may include a mesh interface component and a port identifier, and one or more information elements selected from the group consisting of a payload, a target node identifier, a target type identifier, an information type identifier, a linear identifier, and a protocol identifier.

Node identification allocation in a multi-tile system with multiple derivatives

A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

Peripheral component interconnect attributes shared using address bits

In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

Payload cache

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Caching for heterogeneous processors

One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of the tiles.

Hardware engine for configuration register setup

A multiprocessor device includes cores and at least one ingress-write ordering circuitry (IWOC) including first and second counters associated with first and second destinations. The IWOC is configured to assign sequential numbers to write transactions received from a source, according to an order of reception at the IWOC, and to forward the write transactions from the IWOC to the first and second write-transaction destinations, while preserving the order, by incrementing the first and second counters such that both the first counter and the second counter track a sequential number of a next write transaction that the IWOC will forward, forwarding a first write transaction to the first destination only provided that the sequential number of the first write transaction matches the first counter, and forwarding a second write transaction to the second destination only provided that the sequential number of the second write transaction matches the second counter.

Write reordering in a multiprocessor system

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an 'Owned' state and a Forward state together with protocol mechanism for handling various memory requests.

Computing in parallel processing environments

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also discussed are techniques to add new capabilities to protocols, such as the CHI protocol to achieve 'Total Store Order' (TSO) among multiple devices, such as PCI Express devices, in a cost effective manner.

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Atomic operations in PCI express

Transaction layer packet formatting

Growing community of inventors

Uxbridge, MA, United States of America

Mark B Rosenbluth