International Business Machines Corporation

Northrop Grumman Systems Corporation

Raytheon Bbn Technologies Corp.

Glocbalfoundries Inc.

Mark B Ketchen

Manjul Bhushan

John Francis Bulzacchelli

Josephine B Chang

William Joseph Gallagher

Edward P Maciejewski

Gerald Warren Gibson, Jr

Chandrasekharan Kothandaraman

Matthias Steffen

Dale J Pearson

Chin Kim

Christopher B Lirakis

John R Kirtley

Edward J Nowak

Jay Michael Gambetta

Wilfried Haensch

John Albrecht Ott

Chad Tyler Rigetti

Stefan Harrer

Stanislav Polonsky

Brian L Ji

Mark B Ritter

Alexey Y Lvov

Stanislav Vladimirovich Polonsky

Jean-Marc Halbout

Karen M G V Gettings

John J Ellis-Monaghan

Jed Hickory Rankin

Andres Bryant

Paul Andrew Moskowitz

Qingqing Liang

Derek L Knee

Chao-Kun Hu

Oliver Desmond Patterson

Mark A Jaso

Randall M Burnett

Peter Edwin Cottrell

Kevin McStay

Ishtiaq Ahsan

Carl J Anderson

Michael R Scheuermann

Keith C Stevens

Daniel R Grischkowsky

Alan W Kleinsasser

Shwetank Kumar

Richard Lazarus

Irl N Duling, Iii

Sarah H Blanton

Edge-sensitive, state-based single flux quantum (SFQ) based circuitry and related methods convert return-to-zero (RZ) or non-return-to-zero (NRZ) encoded SFQ-pulse-based signals to bilevel NRZ phase signals that can subsequently be converted to bilevel voltage signals by an output amplifier (OA). The SFQ-based circuitry can be integrated with a current amplification stage of a driver that can be coupled to a stage of the OA. The SFQ-based circuitry can be made to be compatible with RQL-encoded input signals that can be either RZ or NRZ. The SFQ-based circuitry can thus be compatible with both wave-pipelined (WPL) and phase-mode (PML) RQL circuitry. Because the SFQ-based circuitry and related methods are edge-sensitive and state-based, they can function at system clock rates in excess of 1 GHz with reduced glitches and improved bit error rates as compared to other superconducting RZ-NRZ conversion circuitry and methods.

Circuits for converting SFQ-based RZ and NRZ signaling to bilevel voltage NRZ signaling

A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.

Trilayer Josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

A probabilistic digitizer for extracting information from a Josephson comparator is disclosed. The digitizer uses statistical methods to aggregate over a set of comparator readouts, effectively increasing the sensitivity of the comparator even when an input signal falls within the comparator's gray zone. Among other uses, such a digitizer may be used to discriminate between states of a qubit.

Single-flux-quantum probabilistic digitizer

Trilayer josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

A quantum information processing system includes a first composite quantum system, a second composite quantum system, a plurality of electromagnetic field sources coupled to the system and an adjustable electromagnetic coupling between the first composite quantum system and the second composite quantum system.

Modular array of fixed-coupling quantum systems for quantum information processing

A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M) in the integrated circuit device.

Single level of metal test structure for differential timing and variability measurements of integrated circuits

A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.

In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Hybrid superconducting-magnetic memory cell and array

A structure and method is provided for testing a 2-dimensional array of electrical devices, such as a 2-dimensional array in the first metal level (M1) of an electronic structure. The method for testing the 2-dimensional array provides a parallel test approach. The test structure provides a plurality of test pad structures to implement the parallel test approach. The test pad structures may include field effect transistors.

Active 2-dimensional array structure for parallel testing

Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.

Semiconductor devices having nanochannels confined by nanometer-spaced electrodes

A device includes a volume bounded by electromagnetically conducting walls, an aperture in a bounding wall of the electromagnetically conducting walls, a plurality of quantum systems disposed within the volume and an electromagnetic field source coupled to the volume via the aperture.

Array of quantum systems in a cavity for quantum computing

Growing community of inventors

Hadley, MA, United States of America

Mark B Ketchen