Altera Corporation

Mark Ari Teper

Steven Caranci

Mark Bourgeault

Ketan Padalia

Shawn Malhotra

Przemek Guzy

Alexander Grbic

A system evaluates a hierarchical name set such as names produced by hardware descriptor language (HDL) synthesis and generates shorter, unambiguous names for each of the hierarchical names in the name set. A directed graph and/or a tree is generated using a hierarchical name set. Each name is evaluated using the directed graph and/or tree to identify hierarchical components or tokens of the name required in the short name. Name length can be reduced even in a system having large numbers of common hierarchies.

Generation of readable hierarchical path identifiers

A method for generating a design for a system to be implemented on a target device includes compiling the design. Information used to make a compilation decision on the design is stored. A strategy to improve timing closure on a signal path on the design is derived using the information.

Method and apparatus for performing automated timing closure analysis for systems implemented on target devices

A graphical block-based design exploration tool displays multiple views of a chip design. These views may include a logical view, physical view, hierarchy view, and a timing display view, displayed side-by-side or sequentially with or without animation. Various entities and their relationships to each other are displayed in these different view arrangements to allow a user to quickly grasp the entire design and to perform design techniques such as partitioning and floor planning. The display properties are user configurable to organize the information based on user preferences.

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Toronto, Canada

Mark Ari Teper