International Business Machines Corporation

Mark Anthony Check

John Stephen Liptay

Charles Franklin Webb

Mark S Farrell

Timothy John Slegel

Bernard Charles Drerup

Michael Grassi

Vincenzo Condorelli

Chung-Lung K Shum

Jennifer A Navarro

Eric M Schwarz

Ronald Morton Smith, Sr

Bruce C Giamei

Todd Weston Arnold

Gary E Strait

Barry Watson Krumm

Sundeep Chadha

Robert Brett Tremaine

Christopher A Krygowski

Aaron Tsai

Nihad Hadzic

Ronald M Smith

Klaus Meissner

Diana Lynn Orf

Eberhard Engler

William Santiago Fernandez

Hong Deng

Dan F Greiner

Fadi Y Busaba

Thomas Anthony Gregg

Brian Robert Prasky

Charles W Gainey, Jr

Damian Leo Osisek

Steven R Carlough

David F Craddock

Pak-kin Mak

Jane Helen Bartik

Prabhakar Nandavar Kudva

John Robert Ehrman

John G Rell, Jr

Peter Jeremy Relson

Dean G Bair

Brian B Moore

Mike Stephen Fulton

Jonathan Yang Chen

Andrew R Ranck

Hanno Ulrich

Pia Naoko Sanda

Jennifer Serena Navarro

Thomas G Foote

Steven B Risch

Evangelyn K Smith, Legal Representative

Frank Tanzi

Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.

Customer load of field programmable gate arrays

In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.

Arbitration in an SRIOV environment

A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.

Memory error isolation and recovery in a multiprocessor computer system

An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level 'gate-level' netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance.

Verification of soft error resilience

A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.

Performing a perform timing facility function instruction for synchronizing TOD clocks

A system to determine fault tolerance in an integrated circuit may include a programmable logic device carried by the integrated circuit. The system may also include a configurable memory carried by the programmable logic device to control the function and/or connection of a portion of the programmable logic device. The system may further include user logic carried by said programmable logic device and in communication with a user and/or the configurable memory. The user logic may identify corrupted data in the configurable memory based upon changing user requirements.

System to determine fault tolerance in an integrated circuit and associated methods

A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory. The processor is capable of performing a PTFF instruction comprising: obtaining a function code specified in a first general register, the function code for identifying any one of a query function or a control function to be performed; obtaining, from a second general register, a memory address of a parameter block; responsive to the function code specifying a query function, storing timing information of the computer system in the parameter block according to the specified query function; responsive to the function code specifying a control function, using timing information obtained from the parameter block to perform the specified control function; and setting a condition code value indicating an outcome of the specified function.

Performing a perform timing facility function instruction for sychronizing TOD clocks

The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.

Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance

Method, system and computer program product for enhanced shared store buffer management scheme for differing buffer sizes with limited resources for optimized performance

A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

Utilizing programmable channels for allocation of buffer space and transaction control in data communications

In a computer system with multiple chips connected via a connection module with high speed elastic interface buses that support bus repair is enhanced by use of a spare net. Support is provided to ensure that the spare net can be tested in the same way that every normal bus net can be tested at all supported environments. It ensure that the system controller can find out what connections are bad and how to apply the controls to repair them for all tests and in the field for the customer.

System and method to support use of bus spare wires in connection modules

A method is provided for recording a list of facilities available to a program executing on an information processing system. In such method a storage location and a length of data are defined for recording the list of facilities by a program being executed on the information processing system. An instruction is issued by the program for determining the available facilities and recording the list of available facilities in accordance with the defined storage location and data length. A processor executes the instruction to determine the available facilities and record the list of facilities in accordance with the defined storage location and defined data length. The recorded list of facilities can then be read by the first program.

Enhanced un-privileged computer instruction to store a facility list

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Hopewell Junction, NY, United States of America

Mark Anthony Check