Lucent Technologies Inc.

Agere Systems Inc.

Lsi Corporation

Mark Andrew Bickerstaff

Benjamin John Widdup

Christopher John Nicol

Graeme Woodward

Bing Xu

Ran-Hong Yan

Yi-Chen Li

Yunxin Li

Mark Barry

Linda Mary Davis

Chris Nicol

Bejamin John Widdup

Graeme Edwin Pope

A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity.

Modified branch metric calculator to reduce interleaver memory and improve performance in a fixed-point turbo decoder

A method includes storing at least one user datum received from a user in a secure storage portion of a memory within a mobile communication device. Authentication information is received into the mobile communication device. The at least one user datum is transmitted from the mobile communication device to a recipient in response to entry of the authentication information, while preventing the user of the mobile communication device from reading the at least one user datum.

Information security and delivery method and apparatus

Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of the plurality of sub-matrices has a single entry. Each of the sub-matrices has at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, wherein one or more of the memory elements may be selectively disabled. The Phi-nodes may be selectively disabled, for example, at run-time. The Phi-node optionally further comprises a multiplexer in order to provide a variable parity check matrix.

Method and apparatus for block and rate independent decoding of LDPC codes

An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly 'trains' itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.

Pre-emptive interleaver address generator for turbo decoders

A turbo decoder having two modes of operation decodes received information as per an N-state Radix-K trellis where N and K are integers equal to 1 or greater. The turbo decoder uses an in-line addressing technique that allows it to operate as a Serial Convolutional Code decoder in the first mode of operation and a Parallel Convolutional Code decoder in the second mode of operation. The decoder uses an in line addressing technique that allows it to use the same block of memory to store and retrieve states of the trellis as it processes received information. The turbo decoder can also operate as per an N-state Radix-K trellis where N is an integer equal to 2 or greater and K is an integer equal to 4 or greater.

Unified serial/parallel concatenated convolutional code decoder architecture and method

The present invention discloses a single unified decoder for performing both convolutional decoding and turbo decoding in the one architecture. The unified decoder can be partitioned dynamically to perform required decoding operations on varying numbers of data streams at different throughput rates. It also supports simultaneous decoding of voice (convolutional decoding) and data (turbo decoding) streams. This invention forms the basis of a decoder that can decode all of the standards for TDMA, IS-95, GSM, GPRS, EDGE, UMTS, and CDMA2000. Processors are stacked together and interconnected so that they can perform separately as separate decoders or in harmony as a single high speed decoder. The unified decoder architecture can support multiple data streams and multiple voice streams simultaneously. Furthermore, the decoder can be dynamically partitioned as required to decode voice streams for different standards.

Reconfigurable architecture for decoding telecommunications signals

A Log Map processor that processes information in accordance with the Log MAP algorithm using an N-state Radix-K trellis where K is an integer equal to 4 or greater and N is an integer equal to 2 or greater. The Log Map processor comprises branch and path metric calculators designed with LogSum operators. The LogSum operators used and Add-Compare-Select architecture that is based on an approximation of the Jacobian definition of the LogSum operation. The Log Map processor is thus able to process relatively more information per unit time.

Higher radix Log MAP processor

In the method of generating a pseudo random number, pseudo random numbers equal to pseudo random numbers generated from a pseudo random number generation function indexed by orders of two are stored. Then, a pseudo random number is generated based on the stored pseudo random numbers.

Method and apparatus for generating a pseudo random number

An apparatus and a method for calculating in-place pat metric addressing far a trellis processing arrangement are provided. An arrangement of cascaded multiplexers and stores receives a known input sequence of path metrics. The input sequence of path metrics is manipulated such that certain of the path metrics are delayed in the stores by a clock cycle, whilst the remaining path metrics are presented to the cascaded banks of multiplexers. In this manner, the input sequence of path metrics is continuously processed to produce a desired output sequence of path metrics. Advantageously, embodiments of the apparatus and method may be practiced on either a forward trellis or a reverse trellis.

Method and apparatus for path metric processing in telecommunications systems

The present invention discloses a butterfly processor capable of performing convolutional decoding and LogMAP decoding in telecommunications systems. First and second add-compare-select modules are provided for receiving input path metrics. A branch metric calculator is also provided for receiving input data and extrinsic data. The branch metric calculator generates output branch metrics to each of the first and second add-compare-select modules. Each of the add-compare-select modules includes a log-sum correction means coupled to compare and select components. A controllable switch selectively couples outputs of the select components and the log-sum corrections means to enable either one of convolutional or LogMAP decoding.

Butterfly processor for telecommunications

In the method of generating an interleaved address, each 2^i mod (p&#x2212;1) value for i=0 to x&#x2212;1 is stored. Here, p is a prime number dependent on a block size K of a data block being processed and x is greater than one. An inter-row sequence number is multiplied with a column index number to obtain a binary product. Both the inter-row sequence number and the column index number are for the block size K and the prime number p. Then, each binary component of the binary product is multiplied with a respective one of the stored 2^i mod (p&#x2212;1) values to obtain a plurality of intermediate mod value. An intra-row permutation address is generated based on the plurality of intermediate mod values, and an interleaved address is generated based on the intra-row permutation address.

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Carlingford, Australia

Mark Andrew Bickerstaff