Altera Corporation

Mark Andrew Banke

Adam J Wright

Joseph W Foerstel

Ken A Ito

Chung Fu

Aman Aflaki Beni

William H Hata

John M Dicosola

Junzhao J Lei

A system for testing a device under test (DUT), in which electrical coupling among a module board, a low profile connector, and, a DIB is established by applying a pressure on the module board toward the DUT, is provided. The system includes a test head bracket secured inside a test head, the test head bracket includes the module board having a first section including a plurality of connectors to couple a test analyzer to the module board, a second section including a plurality of contacts pads to electrically couple the module board to the DUT, and, a flexible board to enable the first section to be placed at an angle with respect to the second section. The test head bracket also includes a module board stiffener mechanically securing the first section and the second section to the test head and the low profile connector electrically couples the module board to the DUT.

Apparatus for a low-cost semiconductor test interface system

A test probe may have signal and ground probe pins. During testing of an integrated circuit die, the signal and ground probe pins may contact pads on the die. A printed circuit board may have conductive pads and traces that route signals between a tester and the probe pins. The probe pins may be supported by a ring-shaped conductive epoxy support structure. The ground probe pins may be uninsulated within the conductive epoxy support structure, so that the ground probe pins are grounded along their length to the support structure. The signal probe pins may be insulated within the support structure. Coaxial cable shielding may be provided on the signal pins between an outer wall portion of the support structure and the printed circuit board.

Probe cards with minimized cross-talk

Systems and methods are provided for marking integrated circuit defects on wafers to facilitate failure analysis. A wafer containing integrated circuits can be tested using a tester. Test data from the tester can be analyzed using integrated circuit design files to identify suspected faults. A fault location program can be used to identify the physical location of the faults. The fault location program uses information on the faults identified and CAD file information on the physical layout of the integrated circuit to map identified faults to actual physical positions. The fault location program may also generate laser control files. The laser control files can be used to control a laser system so that the laser system creates laser marks on the wafer surrounding each of the faults. The marked faults can be polished and examined under an electron microscope or analyzed using other failure analysis tools.

Methods and apparatus for laser marking of integrated circuit faults

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San Jose, CA, United States of America

Mark Andrew Banke