Arm Limited

Mark Allen Silla

Gerard Richard Williams

Peter Guy Middleton

Richard Slobodnik

Michael Thomas Kilpatrick

Arthur R Piejko

Michael L Brauer

John Stuart Kelly

A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way. The processor clock control device comprises: at least two clock signal inputs each operable to receive a clock signal, said clock signals comprising a first and a second clock signal; a sensor operable to sense said first and said second clock signals; a clock signal output operable to output a clock signal for input to a processor; and a clock switching signal input for receiving a switching signal operable to control switching of said clock signal output from said first clock signal to said second clock signal; wherein said processor clock control device is operable on receipt of said clock switching signal to sense said first clock signal and when said first clock signal transitions from a first predetermined level to a second level, said processor clock control device is operable to hold said clock signal output at said second level, and then to sense said second clock signal and when said second clock signal transitions from said second level to said first predetermined level to output said second clock signal.

Switching between clocks in data processing

The present invention relates to a memory device and method for reducing leakage current during a power down mode of operation. The memory device comprises a column of memory cells, with each memory cell being arranged to store a data value, and a pair of bit lines coupled to the column of memory cells. Bit line precharge circuitry is provided for precharging the pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in the column is selected in an evaluate phase following the precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell. In accordance with the present invention, the memory device further comprises power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging the pair of bit lines, and selector circuitry arranged when the memory device is to enter the power down mode to ensure that none of the memory cells in the column are selected. It has been found that by taking this approach during the power down mode of operation, a significant reduction in the leakage current is observed.

Reducing leakage current in a memory device

A cache memory 18 is formed of a content addressable memory 20 and a cache RAM 22. The content addressable memory 20 is divided into two or more sections by an AND gate array 28 that serves to selectively either block or unblock the bit lines 26 that supply an input data word to the bit storage and comparison cells 34 of the content addressable memory 20. The generation of match signals for each section is also selectively blocked by preventing the match signal discharge to ground. The match signals from a blocked section are not passed to the RAM 22. The AND gate array 28 and match signal disable may be controlled by the least significant bit of the input data word, higher order bits of the input data word or may be controlled by a bit selected by program control from among the bits of the input data word. When a portion of the bit lines 26 are blocked by the AND gate array 28, then the capacitance of the bit lines 26 that need to be driven is reduced and the number of match lines discharged is halved thereby reducing power consumption.

Bit line and/or match line partitioned content addressable memory

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Hutto, TX, United States of America

Mark Allen Silla