Freescale Semiconductor,inc.

Motorola Corporation

Mark Allen Gerber

Shawn M O'Connor

Trent A Thompson

Sohrab Safai

Bennett Joiner

Dae Y Hong

Jose Antonio Montes De Oca

Jean Desiree Miller

A package device () has one integrated circuit () in a cavity () in a package substrate () and electrically coupled to one side () of the package substrate. A second integrated circuit () is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit () or more may be mounted on the second integrated circuit. Pads () useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.

Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing

A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.

Multi-die semiconductor package

A packaged semiconductor device () has a first integrated circuit die () having a top surface with active electrical circuitry implemented thereon. The first die () is mounted in a cavity () of a first heat spreader (). A second die () having electrical circuitry implemented on a top surface is attached to the top surface of the first die (). Both of the die (and) are electrically connected to a substrate () mounted on the first heat spreader (). A second heat spreader () is mounted on the top surface of the second die (). The second heat spreader () provides an additional path for thermal dissipation of heat generated by the second die ().

Packaged semiconductor device and method of formation

A package substrate () has a first surface, a second surface opposite a first surface, and a cavity () formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die () is placed in the cavity, and a conductive material () is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer () may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.

Low profile semiconductor device having improved heat dissipation

A semiconductor die has three rows or more of bond pads with minimum pitch. The die is mounted on a package substrate having three rows or more of bond fingers and/or conductive rings. The bond pads on the outermost part of the die (nearest the perimeter of the die) are connected by a relatively lower height wire achieved by reverse stitching to the innermost ring(s) or row (farthest from the perimeter of the package substrate) of bond fingers. The innermost row of bond pads is connected by a relatively higher height wire achieved by ball bond to wedge bond to the outermost row of the bond fingers. The intermediate row of bond pads is connected by relatively intermediate height wire by ball bond to wedge bond to the intermediate row of bond fingers. The varying height wire allows for tightly packed bond pads. The structure is adaptable for stacked die.

Packaged semiconductor with multiple rows of bond pads and method therefor

A multi-chip assembly (100) uses a clip (110) to retain multiple integrated circuits (124-130) to an assembly substrate (140). The use of a thermal medium between the integrated circuits and the heat sinks (120, 122) allows the assembly to be disassembled for rework purposes. The clip contains edge clamps (112), alignment rails (114), and alignment features (116, 316, 416) to properly orient the clip, heat sink, integrated circuits, and assembly substrate.

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Austin, TX, United States of America

Mark Allen Gerber