Maxim Integrated Products, Inc.

Alcatel Lucent

Mark Alan Lovell

Robert Michael Muchsel

Donald Wood Loomis, Iii

Hung Thanh Nguyen

Edward Tangkwai Ma

Nancy Kow Iida

Donald W Loomis

Edward Tang K Ma

Michael Anthony Quarles

Mandana Nooraee Parker

Paul E Irek

In-flight operations in an inbound data path from a source memory to a convolution hardware circuit increase computational throughput when performing convolution calculations, such as pooling and element-wise operations. Various operations may be performed in-line within an outbound data path to a target memory. Advantageously, this drastically reduces extraneous memory access and associated read-write operations, thereby, significantly reducing overall power consumption in a computing system.

Systems and methods for performing in-flight computations

Dynamic data-dependent neural network processing systems and methods increase computational efficiency in neural network processing by uniquely processing data based on the data itself and/or configuration parameters for processing the data. In embodiments, this is accomplished by receiving, at a controller, input data that is to be processed by a first device in a first layer of a sequence of processing layers of a neural network using a first set of parameters. The input data is analyzed to determine whether to modify it, whether processing the (modified) data in a second layer would conserve at least one computational resource, or whether to apply a different set of parameters. Depending on the determination, the sequence of processing layers is modified, and the (modified) data are processed according to the modified sequence to reduce data movements and transitions, thereby, conserving computational resources.

Dynamic data-dependent neural network processing systems and methods

Systems and methods reduce power consumption in embedded machine learning hardware accelerators and enable cost-effective embedded at-the-edge machine-learning and related applications. In various embodiments this may be accomplished by using hardware accelerators that comprise a programmable pre-processing circuit that operates in the same clock domain as the accelerator. In some embodiments, tightly coupled data loading first-in-first-out registers (FIFOs) eliminate clock synchronization issues and reduce unnecessary address writes. In other embodiments, a data transformation may gather source data bits in a manner that allows loading full words of native bus width to reduce the number of writes and, thus, overall power consumption.

Systems and methods for reducing power consumption in embedded machine learning accelerators

Described herein are systems and methods for efficiently processing large amounts of data when performing complex neural network operations, such as convolution and pooling operations. Given cascaded convolutional neural network layers, various embodiments allow for commencing processing of a downstream layer prior to completing processing of a current or previous network layer. In certain embodiments, this is accomplished by utilizing a handshaking mechanism or asynchronous logic to determine an active neural network layer in a neural network and using that active neural layer to process a subset of a set of input data of a first layer prior to processing all of the set of input data.

Systems and methods for reducing memory requirements in neural networks

Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy needs to be anticipated or even calculated to a certain degree. Accordingly, power supply output may be optimized according to actual energy needs of compute circuits. In certain embodiments this is accomplished by proactively and dynamically adjusting power-related parameters according to high-power and low-power operations to benefit a machine learning circuit and to avoid wasting valuable power resources, especially in embedded computing systems.

Power control systems and methods for machine learning computing resources

Described herein are systems and methods that increase the utilization and performance of computational resources, such as storage space and computation time, thereby, reducing computational cost. Various embodiments of the invention provide for a hardware structure that allows both streaming of source data that eliminates redundant data transfer and allows for in-memory computations that eliminate requirements for data transfer to and from intermediate storage. In certain embodiments, computational cost is reduced by using a hardware structure that enables mathematical operations, such as element-wise matrix multiplications employed by convolutional neural networks, to be performed automatically and efficiently.

Energy-efficient memory systems and methods

An energy-efficient sequencer comprising inline multipliers and adders causes a read source that contains matching values to output an enable signal to enable a data item prior to using a multiplier to multiply the data item with a weight to obtain a product for use in a matrix-multiplication in hardware. A second enable signal causes the output to be written to the data item.

Systems and methods for energy-efficient data processing

Presented are systems and methods that allow hardware designers to protect valuable IP and information in the hardware domain in order to increase overall system security. In various embodiments of the invention this is accomplished by configuring logic gates of existing logic circuitry based on a key input. In certain embodiments, a logic function provides results that are dependent not only on input values but also on an encrypted logic key that determines connections for a given logic building block, such that the functionality of the logic function cannot be determined by reverse engineering. In some embodiments, the logic key is created by decrypting a piece of data using a secret or private key. Advantages of automatic encryption include that existing circuitry need not be re-implemented or re-built, and that the systems and methods presented are backward compatible with standard manufacturing tools.

Systems and methods for enhancing confidentiality via logic gate encryption

Presented are systems and methods that allow hardware designers to protect valuable IP and information in the hardware domain in order to increase overall system security. In various embodiments of the invention this is accomplished by configuring logic gates of existing logic circuitry based on a key input. In certain embodiments, a logic function provides results that are dependent not only on input values but also on an encrypted logic key that determines connections for a given logic building block, such that the functionality of the logic function cannot be determined by reverse engineering. In some embodiments, the logic key is created by decrypting a piece of data using a secret decryption key. Advantages of automatic encryption include that existing circuitry need not be re-implemented or re-built, and that the systems and methods presented are backward compatible with standard manufacturing tools.

The present invention relates to a microcontroller designed for protection of intellectual digital content. The microcontroller includes a secure CPU, a real-time cipher, and a user programmable multi-layer access control system for internal memory realized by programmable nonvolatile memory. Programmable nonvolatile memory allows in-system and in-application programming for the end user. The programmable nonvolatile memory is mainly used for program code and operating parameter storage. The multiple-layer access control is an integral part of the CPU, providing confidentiality protection to embedded digital content by controlling reading, writing, and/or execution of a code segment according to a set of user-programmed parameters. The cipher incorporates a set of cryptographic rules for data encryption and decryption with row and column manipulation for data storage. All cryptographic operations are executed in parallel with CPU run time without incurring additional latency and delay for system operation.

Growing community of inventors

Lucas, TX, United States of America

Mark Alan Lovell