Intel Corporation

Mark A Yarch

Hang T Nguyen

Pankaj Kumar

Byron R Gillespie

John Alan Miller

Marc A Goldschmidt

Timothy J Jehl

Methods and apparatus relating to processing out of order transactions for mirrored subsystems. A first device (that is mirroring data from a second device) includes a cache to track out of order write operations prior to writing data from the write operations to memory. A register may be used to track the state of the cache in response to receipt of a special transaction, which may be a posted transaction or snapshot. The first devise transmits an acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Devices may communicate via a peripheral component interconnect express (PCIe) interconnect, and may include a point-to-point or serial link. Various components may be on the same integrated circuit die. An uninterrupted power supply or batteries may supply power in response to a power failure.

Processing out of order transactions for mirrored subsystems using a cache to track write operations

In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

Mirroring data between redundant storage controllers of a storage system

Briefly, in accordance with one embodiment of the invention, an integrated circuit has two voltage domain regions. The integrated circuit provides for changing the operational voltage of one of the voltage domain regions with respect to the other.

Integrated circuit having various operational modes and a method therefor

An alignment logic circuit transferring segments of data from a first storage device to a second storage device is provided. The alignment logic circuit includes a first and second alignment stages, and an alignment control logic that controls the first and second alignment stages such that the first alignment stage outputs data aligned in a first dimension according to a second configuration, and the second alignment stage outputs data aligned in a second dimension according to the second configuration. A computer system with a DMA controller with a Memory Write and Invalidate logic circuit is provided. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than or equal to a cacheline size, and the current transfer adders is a multiple of the cacheline size. A computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access (DMA) controller is also provided. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus and a DMA IDLE. The error handling logic aborts a DMA transfer when the error signal and the DMA signal are asserted and the retry signal is deasserted.

Direct memory access controller

The present invention provides an alignment logic circuit transferring segments of data from a first storage device to a second storage device. The segments of data are aligned in the first storage device, in a first and second dimension, according to a first configuration. The segments of data are aligned in the second storage device, in the first and second dimension according to a second configuration. The alignment logic circuit includes a first alignment stage, a second alignment stage, and an alignment control logic controls the first alignment stage such that the first alignment stage outputs data aligned in the first dimension according to the second configuration, and the second alignment stage outputs data aligned in the second dimension according to the second configuration. It is also provided a computer system with a DMA controller with a Memory Write and Invalidate logic circuit. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than a recall with a cacheline size, and the current transfer adders is a multiple of the cacheline size. The present invention also provides a computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access controller (DMA). The DMA performs DMA transactions between the first and second buses. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus. The error handling logic aborts a DMA transfer when the error signal is asserted and the retry signal is deasserted.

System for transferring data segments from a first storage device to a

A computer system is provided including a local memory, a local bus coupled to the local memory, a peripheral bus and a direct memory access (DMA) controller. The DMA controller performs DMA transfers of data between the local bus and the peripheral bus. The DMA includes a DMA queue for storing data to be transferred and a bus ownership status circuit for determining bus ownership status of the DMA controller. The DMA controller further includes a local bus interface circuit coupled to the DMA queue and to the status circuit for halting the transfer of data from the local bus to the DMA queue without relinquishing DMA ownership over the local bus when the DMA queue is full and the status circuit indicates that the DMA controller has ownership over both the peripheral bus and the local bus.

Growing community of inventors

Chandler, AZ, United States of America

Mark A Yarch