International Business Machines Corporation

University of Notre Dame Du Lac

Mark A Wistey

Siyuranga O Koswatta

Patrick Fay

Huili (Grace) Xing

Alan C Seabaugh

Guangle Zhou

Yeqing Lu

A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.

Low voltage tunnel field-effect transistor (TFET) and method of making same

Growing community of inventors

South Bend, IN, United States of America

Mark A Wistey