Texas Instruments Corporation

Mark A Stambaugh

Stephen P Sacarisen

Michael W Patrick

Ki S Chang

William H Brodhead

A test circuit (40) fabricated in an integrated circuit and connected to an I/O pin (36) of the packaged device (32) for providing information indicative of substrate process parameters. The test circuit (40) comprises a test transistor (24) connected to a pin (36) of the packaged device (32), and an isolation circuit (52) responsive to a signal on an input test terminal (48) for activating the test transistor (24). The isolation circuit (52) is responsive to the absence of the test signal for isolating the test transistor (24) from the pin (36), and thus isolating it from other functional circuitry (54) of the integrated circuit which is also connected to the pin (36).

Packaged semiconductor device with test circuits for determining

A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is disclosed. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device therein which operates relatively independently from the host CPU, and which is coupled to the main memory by the system bus, includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data

A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective pairs of input data lines. Each decode circuit has an odd and even output line for providing output signals in response to odd or even number of 1's (or 0's) on an associated pair of row lines, respectively. The circuit includes a precharge discharge circuit coupled to the prestage circuit for generating a first parity signal in response to an odd number of 1's being on the input data lines and a second parity signal in response to an even number of 1's being on the input data lines.

Polyphase parity generator circuit

A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency 'f' into two non-overlapping complementary clock signals of frequency 'f' and a shift register circuit. The shift register circuit is coupled to the signal splitting means and generates an output clock signal of frequency f/n in response to the two complementary clock signals. The output clock signal has a duty cycle equal to ((n-1)/2+D.sub.in)/n where D.sub.in is the duty cycle of the incoming clock signal. The output duty cycle is substantially independent of processing and operating conditions.

Frequency divide by N circuit

A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

Microprocessor with integrated CPU, RAM, timer, bus arbiter data for

A microprocessor device with an on-chip integrated auto-loaded timer is used in an adapter for a communications loop of the token-passing local area network type. The network has a number of stations coupled to a closed one-way signal path, and each station has a host processor with a host CPU and memory. The microprocessor device with integrated auto-loaded timer is part of an adapter coupled to the host processor. A message frame to be transmitted is copied into a local read/write memory in the adapter by way of the host system bus and a local bus, under initiation by the host CPU. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station has access to the loop (i.e., receives a free token) the transmit-and-receive controller copies the message frame from the local read/write memory to the outgoing signal path, converting from parallel to serial. When the transmit-and-receive controller receives a message addressed to this station, it converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus, interrupting the local CPU. The message frame is then copied from the local read/write memory to the main memory.

Microprocessor device with integrated auto-loaded timer

A read-only memory includes an array of rows and columns of memory cells with row lines and column lines associated with the array. The row lines are partitioned into groups that provide bits of a word on a number of output lines. Each group consists of an output line and a first voltage line with a plurality of row lines in between. A row selector is provided that receives an address signal for selecting a particular row in each group and connects a row line on one side of the selected row to the first voltage line and connects the row line on the other side of the row to the output line. A row precharge circuit is provided for precharging the row lines prior to the connection of a row line to an output line. Also provided is a column select circuit for receiving an address signal for connecting a particular column line to a second voltage line and for connecting one or more of the remaining column lines to one of the first voltage lines in order to reduce coupling.

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Houston, TX, United States of America

Mark A Stambaugh