Micron Technology Incorporated

Mark A McQueen

Luan C Tran

Chandra V Mouli

Robert B Kerr

The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1&#xd7;10atoms/cmwith n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

Semiconductor constructions, and methods of forming semiconductor constructions

Semiconductor constructions

Apparatus and methods forming electrostatic discharge and electrical overstress protection devices for integrated circuits wherein such devices include shared electrical contact between source regions and between drain regions for more efficient dissipation of an electrostatic discharge. The devices further include contact plugs and contact lands which render the fabrication of the devices less sensitive to alignment constraint in the formation of contacts for the device.

ESD/EOS protection structure for integrated circuit devices

ESD/EOS protection structure for integrated circuit devices and methods of fabricating the same

The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1&times;10 atoms/cm with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

Methods of forming isolation regions associated with semiconductor constructions

An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.

Double LDD devices for improved DRAM refresh

Double LDD devices for improved dram refresh

A method of fabricating a stacked capacitor memory cell having a reduced leakage storage node includes the steps of providing a P-type substrate, forming wordlines on a thin gate oxide layer and a field oxide layer, and forming a first conformal TEOS oxide layer. The P-type substrate is doped with an N-type dopant directly through the first TEOS oxide layer to form two N-type diffused areas, which are the first and second current terminals of the memory cell access transistor. A second conformal TEOS oxide layer is deposited. The oxide layers are etched to form a buried contact window above the storage node of the memory cell. The exposed portion of the N-type diffused area forming the memory cell storage node is subsequently doped with germanium through the buried contact window to suppress any outdiffusion due to the doping of subsequently formed layers, such as the first plate of a stacked polysilicon capacitor. The first plate of the stacked capacitor is formed above the buried contact window, and is in contact with the germanium and N-type dopant diffused area. Although the first plate of the stacked capacitor is heavily doped, outdiffusion is limited by the action of the germanium implant.

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Boise, ID, United States of America

Mark A McQueen