Rockwell Collins, Inc.

Rockwell International Corporation

Mark A Kovalan

Douglas Robert Johnson

Mark Clifford Singer

David A Miller

Bryon L Wiscons

John L Persick

Daniel E Mazuk

John W Roltgen

James J Corcoran

Eric J Danielson

Samir S Hemaidan

Peter J Morgan

Nicholas H Bloom

James E Sisson

David C Matthews

Douglas L Bader

Shawn M Stanger

John William Roltgen, Iii

Ronald W Aull

Stephen I Kotalik

Gregory E Dunn

Jimmie L Fisher

Corydon J Carlson

Cleveland C Gilbert

A homomorphic encryption based high integrity computing system including a processing system including a single-string computation channel configured to receive encrypted input data from at least one data source. The processing system includes at least one processor hosting at least one hosted function. The processor is configured to provide high integrity homomorphic encryption-based computations thereon. This enables isolated channel computations within a single physical computation channel. The at least one processor provides encrypted output data, wherein the encrypted output data is configured to enable computational integrity validation by a receiver.

Homomorphic encryption based high integrity computing system

A system includes a first plurality of processors, a second plurality of processors dissimilar from the first plurality of processors, a first arbitration device coupled to the first plurality of processors, and a second arbitration device coupled to the second plurality of processors. The first arbitration device and the second arbitration device is configured to receive event data, store the received event data, and to output the received event data at substantially a same time. At least one processor of the first plurality of processors and at least one processor of the second plurality of processors are configured to access the event data.

Synchronization mechanisms for high-integrity computing

A control system for an aircraft including first and second lanes having respective first and second processors dissimilar to one another and configured to output respective first and second computation data. At least one programmable logic device may be configured to receive the first computation data output and the second computation data output, determine a difference therebetween, and transmit a corrective computation data output to the first processor and the second processor via respective feedback loops if the difference between the first computation data output and the second computation data output exceeds a predetermined threshold value.

System and method for maintaining system integrity in control systems having multi-lane computational differences

A method for testing processors includes generating, from a set of input bits, a first set of machine data bits in a first processor and a second set of machine data bits in a second processor dissimilar to the first processor, and comparing the first and second sets of machine data bits to output a first comparison result. The method also includes generating, from a third set of machine data bits, a first and second sets of machine result bits, and comparing the first and second sets of machine result bits to output a second comparison result. The method further includes generating, from a fourth set of machine data bits, a first and second sets of output bits, and comparing the first and second sets of output bits to output a third comparison result. The method also includes determining whether the first and second processors operate substantially similar to each other based on at least one of the first, second, and third comparison results.

Method for testing capability of dissimilar processors to achieve identical computations

The present disclosure is directed to a passive optical avionics network system and method. A avionics network system may comprise: (a) a passive optical network, the passive optical network comprising an optical repeater; and (b) an avionics module operably coupled to the passive optical network. An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) an optical repeater; (c) at least one optical network unit (ONU); and an avionics module operably coupled to the at least one ONU. A method for avionics network communication may comprise: (a) receiving optical avionics data signals; (b) monitoring the optical avionics data signals for compliance with a communications protocol; and (c) regulating transmission of the optical avionics data signals according to compliance with the communications protocol.

Passive optical avionics network including optical repeater

The present disclosure is directed to a passive optical avionics network system and method. A passive avionics network may comprise: (a) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the OLT and the ONU; and (d) an avionics module operably coupled to the ONU. An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the LRU and the ONU; and (d) an avionics module operably coupled to the ONU. A method for avionics network communication may comprise: (a) providing avionics data; (b) transmitting the avionics data via a fiber optic network; (c) receiving the avionics data; and (d) controlling functionality of an avionics module according to the avionics data.

Passive optical avionics network

A flight control system includes an output device, a first processor, and a second processor. The second processor is dissimilar to the first processor. The flight control system also includes a first arbitration device coupled to the first processor and a second arbitration device coupled to the second processor. The second arbitration device is configured to coordinate transaction synchronization with the first arbitration device and the first arbitration device is configured to coordinate transaction synchronization with the second arbitration device. A comparator processor is coupled to the first arbitration device and the second arbitration device. The comparator processor is configured to compare transaction synchronized outputs of the first and second processors and the comparator processor effectuates a command to the output device if the comparison is valid.

Dissimilar processor synchronization in fly-by-wire high integrity computing platforms and displays

A method of comparing output information from dissimilar processors includes storing a task in a first memory and storing the task in a second memory at substantially the same time as the first memory. The time of the storing being is controlled by a first arbitration logic and a second arbitration logic. The method also includes receiving the task by a first processor from the first memory and receiving the task by a second processor from the memory at substantially the same time as the first processor. The time being received is controlled by a first arbitration logic and a second arbitration logic. The second processor being dissimilar to the first processor. The method further includes computing a first output by the first processor based on the task and computing a second output by the second processor based on the task. The method still further includes, synchronizing the first and second outputs so that the first and second outputs are output at substantially the same time. The synchronizing is controlled by the first and second arbitration logic.

High integrity computing via input synchronization systems and methods

A data transfer mechanism for directing data signals from signal-producing elements to signal-receiving elements is disclosed. The data transfer mechanism includes a plurality of input ports, with each input port being connected to a signal-producing element, and a plurality of output ports, with each output port being connected to a signal-receiving element. Each data signal that enters the data transfer mechanism through one of the plurality of input ports has data identification information associated therewith. The, data transfer mechanism directs the data signal to at least one of the plurality of output ports according to the data identification information associated with the data signal.

Flexible I/O subsystem architecture and associated test capability

A bus system including a bus user apparatus and a method for communicating via the bus system are disclosed. The bus user apparatus includes means for means for selectively coupling a transmitter to the transmission line according to a protocol of the bus system. The bus system provides bi-directional communication over a single transmission line. The transmitter of the transmitting device is coupled to the transmission line during transmission. Upon completion of transmission, the transmitting device sends a permission to transmit signal to the next transmitting device according to the protocol, and decouples its transmitter from the transmission line. The next transmitting device couples its transmitter to the transmission line and begins transmission of data. Multiple bus users, both transmitters and receivers, are accommodated by the bus system, and bi-directional communication is supported. Further, the data transmission rate may be increased by selectively coupling the transmitter of a receiving device to the transmission line to provide a termination impedance on the transmission line. Higher transmission rates may be accommodated without a termination impedance; if necessary, a termination impedance may be applied. If necessary, the output voltage of the transmitter and the sensitivity of the receiver may be adjusted to accommodate the higher transmission rates. The bus system may also accommodate larger sized words. The bus system is compatible with previously existing systems compliant with an ARINC standard while providing increased capability.

Data bus

A circuit and technique of operation thereof are disclosed for a multimaster CPU system wherein a memory may be accessed during program operation in an average time less than that of the memory access time specification. This technique has particular usefulness in programs contained in relatively slow read-only-memory wherein a significant portion of the addresses related to memory are sequential. In optimum utilization, each master CPU has a dedicated PROM card which can only be enabled by the specified CPU. This configuration prevents additional master CPU's from interfering with the time saving benefits of early memory addressing.

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Cedar Rapids, IA, United States of America

Mark A Kovalan