International Business Machines Corporation

National Semiconductor Corporation

Max-planck-gesellschaft Zur Forderung Der Wissenschaften E.v.

Q.sys International, Inc.

Mark A Johnson

Brett Olsson

Fred Gehrung Gustavson

Ramesh Chandra Agarwal

Randall Dean Groves

Brian L Pulito

Thomas H DiStefano

Robert Edward Galbraith

Curtis E Hrischuk

Ellen Marie Bauman

Craig Andrew Lanzen

James Winston Lawwill, Jr

Gary John DeVal

James Bergheim Shearer

Larry W Mayes

Timothy Paul Pickett

Harm Peter Hofstee

Kevin John Nowka

Michael John Brady

Thomas W Keller, Jr

Bishop Chapman Brock

Terry L Lyon

Veera W Deenadhayalan

Mark Scott Kressin

Lawrence V Gregor

Ralph L Hollis, Jr

Mohan Babu Rowlands

Sherman S Wang

Andrew Stewart Lochbaum

John Joseph Forrest

Brian G Cline

Michael T Roble

Robert C Flisik

Jeff Durham

Carlos Querol

A method, system and computer program product for limiting extreme loads and reducing fluctuations in load at session servers. An admission rate controller of a SIP router calculates the 'deflator ratio' equal to the average number of in-dialog messages received over a first fixed interval of time divided by the average number of out-of-dialog messages received over a second fixed interval of time. Further, the admission rate controller calculates the 'dampening ratio' equal to the maximum number of messages allowed over a period of time divided by the number of messages admitted over a previous time interval. When an overload condition has been detected, the admission rate controller calculates the maximum number of out-of-dialog messages to be sent to its associated SIP server based on the deflator and dampening ratios. In this manner, a smoother transition from the overload condition to the non-overload condition may occur.

Limiting extreme loads at session servers

A method, system and computer program product for managing bursts of traffic. A counter, referred to herein as a 'frequency counter,' is incremented during those time intervals an overload condition is detected and is decremented during those time intervals an overload condition is not detected. An overload condition may refer to when the number of out-of-dialog messages exceeds a threshold value corresponding to the maximum number of out-of-dialog messages that should be accepted and forwarded to an associated session server. If the count of the frequency counter exceeds some pre-configured value, then traffic that exceeds the threshold for the overload condition is stopped from being sent to the associated session server. Otherwise, traffic that exceeds the threshold for the overload condition is permitted to be sent to the associated session server. By managing bursts of traffic in such a manner, the effective utilization of session servers is improved.

Managing bursts of traffic in such a manner as to improve the effective utilization of session servers

A system and method is described for providing automated sample preparation for plan view transmission electron microscopy. A sample wafer is microcleaved from a semiconductor wafer and mounted on a first support stub. Then the sample wafer is cut with an automated diamond sawing tool to expose a cross sectional view of the sample wafer. The sample wafer is removed from the first support stub and rotated to orient the sample wafer for plan view imaging. The rotated sample wafer is then remounted on a second support stub and cut with the automated diamond sawing tool to expose a plan view surface of the rotated sample wafer. The remounted sample wafer is subsequently prepared for focused ion beam (FIB) milling and plan view transmission electron microscopy imaging.

System and method for providing automated sample preparation for plan view transmission electron microscopy

A conference server enables collaborative communications among a variety of client processes of varying configurations all operatively coupled over a computer network to each other and to the server. The server receives audio streams from participating client processes in a conference, selects which audio streams are active, and broadcasts one or more of the active audio streams to the client processes participating in the conference depending on the clients receiving capabilities and the conference parameters. The client processes receiving multiple active audio streams perform mixing locally at the client node. Without having to perform mixing at the server, resources are saved and the number of simultaneous participating client processes to the conference may be increased accordingly. The server is further capable of simultaneously accommodating multipoint clients and non-multipoint H.323 clients, as well as operating in multiway and 'push to talk' modes.

Method and apparatus for providing full duplex and multipoint IP audio streaming

A storage controller and associated disk or disk portion where after the controller terminates its access to said disk or disk portion, data integrity problems in the disk or disk portion can be detected. Before host data associated with a write command is written from the cache memory to the disk or disk portion, an identity of the storage controller as a current user of the disk or disk portion and indication that the controller is operating in a mode it stores data in a cache is recorded on the disk or disk portion. If the storage controller is shut down abnormally, the record of the identity of the controller and the indication are not cleared. The storage controller is restarted or rebooted and the record is read to learn that the controller was using the disk or disk portion and operating in the foregoing mode before the shutdown.

System and method for detecting data integrity problems on a data storage device

A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.

Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements

Data in a write cache is coalesced together prior to each destage operation. This results in higher performance by destaging a large quantity of data from the cache with each destage operation. A root item of data is located, and then a working set of data is collected by identifying additional data in the cache that will be destaged to locations in the storage device adjacent to the root item of data. The root item of data may be identified by starting at the location of the least recently accessed data in the cache, and then selecting a root item of data at a lower storage device address than the least recently accessed data, or may be chosen from a larger than average group of data items that were stored together into the cache. To speed execution, data items are added to a working set by, where possible, scanning an queue of data items kept in access order to locate data items at adjacent storage locations.

Destage of data for write cache

A descriptor controlled transmit and receive scatter/gather Direct Memory Access Controller efficiently moves data frames comprised of scattered blocks of data from within memory to a destination interface via a multibyte-wide buffer. The transfer of frames into a transmit buffer and out of a receive buffer is optimized regardless of the total length of the component data blocks and regardless of whether the data blocks include an odd or even number of bytes, whether the data blocks begin at an odd or even address, or whether the data blocks are misaligned with regard to memory width boundaries. A DMAC in accordance with an embodiment of the present invention stores information provided by a descriptor before frame processing takes place. This information in conjunction with steering logic and accumulator registers is used to control the steering and storing of the frame data as it passes through the DMAC to the transmit buffer or from the receive buffer. An alternate embodiment of the present invention performs these functions based on the present values of the descriptor fields. Using predetermined data block descriptor information, the present invention is able to determine on the fly the most efficient way to arrange the bytes of data within the data buffers or memory and concatenate the component data buffers in a buffer or memory to assemble the frames, while inserting frame delineating control words to circumvent the necessity for logic to keep track of these boundaries. The use of the descriptor to steer the data into the transmit buffer or out of the receive buffer allows a simplified hardware implementation as compared to prior art methods that must examine and count the data as it is transferred.

DMA configurable receive channel with memory width N and with steering logic compressing N multiplexors

For error recovery purposes, a backup copy of only a portion of the cache directory is maintained in non-volatile storage. Because only a portion of the cache directory is backup copied, a savings in storage space is realized. The partial copy includes an indication of the storage locations on a storage device for which data is in the cache, and an indication of the state of the data, i.e., whether the data is in process of being read from the cache by the processor, is in process of being written to the cache by the processor, is in the process of being destaged from the cache to the storage device, or none of the above. Only certain changes to the state of the cache cause a backup copy of a portion of the cache directory to be saved; other changes to the state of the cache do not cause the portion of the cache directory to be saved in non-volatile storage. This saves processing time by limiting the number of times that data is copied to the cache.

Backup directory for a write cache

DMA configurable channel with memory width N and with steering logic

In a data processing unit, an instruction is loaded. Such an instruction includes an operation code field for storing an operation code and at least one operand field, where the operand field includes an indirect addressing mode indicator for indicating enablement of an indirect addressing mode. If an indirect addressing mode is enabled, a general purpose register address is selected from an address field in an indirect register. Finally, the data processing unit addresses a selected one of the plurality of general purpose registers utilizing the general purpose register address during the execution of the operation code by the data processing unit.

Method and system for addressing registers in a data processing unit in

A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Method and system in a data processing system for loading and storing

In a data processing unit having a plurality of general purpose registers, an instruction is loaded. Such an instruction includes an operation, and at least one operand field, where the operand field specifies one of a plurality of base registers and a displacement value. To calculate a general purpose register address specified by such an operand field, the displacement value is added to a base value stored in a base register that is specified by a portion of the operand field. Finally, the data processing unit addresses a selected one of the general purpose registers, utilizing the calculated general purpose register address, for execution of the specified operation. Thus, the data processing unit is capable of addressing a larger number of general purpose registers than may be directly addressed utilizing a value represented by a limited number of bits within the operand field.

A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.

Numerically intensive computer accelerator

Growing community of inventors

Austin, TX, United States of America

Mark A Johnson