International Business Machines Corporation

Micron Technology Incorporated

Siemens Aktiengesellschaft

Bae Systems Information and Electronic Systems Integration Inc.

Mark A Jaso

Jeffrey P Gambino

Jack Allan Mandelman

David M Dobuzinsky

William R Tonti

Herbert Lei Ho

David Edward Kotecki

Matthew R Wordeman

Scott David Halle

Erwin Hammerl

Radhika Srinivasan

Craig M Hill

Rainer F Schnabel

Leonard C Stevens, Jr

Thomas R Fisher, Jr

Larry Allan Nesbit

Daniel C Edelstein

Terry L Gilton

Kenneth Parker Rodbell

Subramanian Srikanteswara Iyer

William Joseph Gallagher

Naftali Eliahu Lustig

James Douglas Warnock

Vishnubhai Vitthalbhai Patel

Mark B Ketchen

Bernard S Meyerson

Chao-Kun Hu

Michael D Armacost

Klaus D Beyer

Vlasta A Brusic

Hing Wong

Dale J Pearson

William L Guthrie

Frank Benjamin Kaufman

Paul M Feeney

Scott R Stiffler

Andrew T S Pomerene

Peter D Hoh

Ernest N Levine

Herbert Palm

Timothy J Conway

Alan W Kleinsasser

Hans W Poetzlberger

Peter D Roper

Jeffery Peter Gambino

Paul B Jones

David B Thompson

A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer. Finally, a fourth inner cladding layer followed by a third cladding layer are deposited on the second waveguide layer.

Method for manufacturing multiple layers of waveguides

A method for fabricating selectively coupled optical waveguides on a substrate is disclosed. Initially, a first layer of waveguide material is deposited on a substrate. The first layer of waveguide material is then etched to form multiple level one waveguides and fill shapes. A dielectric layer is deposited on top of the level one waveguides and fill shapes. The surface profile of the dielectric layer deposition tracks the pattern density of the fill shapes. After the surface of the dielectric layer has been polished, a second layer of waveguide material is deposited on the substrate. At least one optically coupled waveguide structure, which is formed by a first level one waveguide and a first level two waveguide, is located adjacent to at least one non-optically coupled waveguide structure, which is formed by a second level one waveguide and a second level two waveguide.

Method for fabricating selectively coupled optical waveguides on a substrate

Apparatus and methods for measuring characteristics of a metallic target as well as other interior surfaces of a sputtering chamber. The apparatus includes a sensor configured to emit an energy beam toward a surface of interest and to detect an energy beam therefrom, the detected energy beam being indicative of parameters of a characteristic of interest of the surface of interest. Quantitative and qualitative characteristics of interest may be determined. A sputtering system including the apparatus and operable according to the methods of the invention is also disclosed.

Apparatus, method and system for monitoring chamber parameters associated with a deposition process

An apparatus and method for measuring the erosion profile of a metallic target in a sputtering device are provided by inserting a thin sensor into a gap between the target and a substrate pedestal. The sensor is configured to emit an energy beam toward the surface of the target and detect a reflection of the energy beam. The sensor may comprise a source element configured to emit a collimated light beam and a plurality of detectors arranged in a linear array. The sensor may also comprise optical fibers configured to reduce the size of the sensor. The detectors are positioned relative to the source element so that one of the detectors in the array will be illuminated by a reflection of the collimated light beam. The distance from the sensor to the target may be derived from the position of the detector illuminated by the reflected beam.

Device for measuring the profile of a metal film sputter deposition target, and system and method employing same

Copper or a copper alloy is removed by chemical-mechanical planarization (CMP) in a slurry of an oxidizer, an oxidation inhibitor, and an additive that appreciably regulates copper complexing with the oxidation inhibitor.

Chemical-mechanical planarization of metallurgy

A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.

Dummy patterns for aluminum chemical polishing (CMP)

In a chemical-mechanical polishing (CMP) process, semiconductor substrates are rotated against a polishing pad in order to planarize substrate layers. The condition of the polishing pad directly affects the polishing rate of material removal and uniformity of removal from the semiconductor wafer. Conditioning of the polishing pad surface with an abrasive improves polishing uniformity and rates, however, it has the detrimental affect of removing a quantity of pad material. A method and apparatus for monitoring polishing pad wear during processing is developed to extend the pad's useful life, and maintain pad uniformity. This is accomplished in the present invention by measuring and monitoring the diminished pad thickness using a non-intrusive measurement system, and creating a closed-loop system for adjusting the chemical-mechanical polishing tool process parameters. The non-intrusive measurement system consists of an interferometer measurement technique utilizing ultrasound or electromagnetic radiation transmitters and receivers aligned to cover any portion of the radial length of a polishing pad surface. The measurement system is sensitive to relative changes in pad thickness for uniformity, and to abrupt changes such as detecting wafer detachment from the CMP wafer carrier.

Method and apparatus for monitoring polishing pad wear during processing

A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.

Low temperature via fill using liquid phase transport

An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

Integrated circuit having a via and a capacitor

The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.

Method of controllably forming a LOCOS oxide layer over a portion of a

Provision of differential etching of layers by, for example, an etch stop layer or implantation, allows a second trough etch to be performed in accordance with a block-out mask (which does not require high accuracy of registration) to provide troughs or recesses of different depths in layers of insulator. When the recesses or troughs are filled by metal deposition and patterned by planarization in accordance with damascene processing, structurally robust conductors of differing thicknesses may be achieved and optimized to enhance noise immunity and/or signal propagation speed in different functional regions of an integrated circuit such as the so-called array and support portions of a dynamic random access memory.

Fabrication of interconnects with two different thicknesses

A process for reducing polish stop erosion includes using a slurry of particles and an alkaline solution. The slurry for reducing polish stop erosion has a reduced solids content, finer particle size, and an increased chemical component. The pH of the slurry is between about 9.5 and 10.5.

Process to reduce localized polish stop erosion

A semiconductor device having areas that are semiconductor on insulator ('SOI') and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.

SOI/bulk hybrid substrate and method of forming the same

A method and apparatus for monitoring polishing pad wear during processing is developed to extend the pad's useful life, and maintain pad uniformity. This is accomplished in the present invention by measuring and monitoring the diminished pad thickness using a non-intrusive measurement system, and creating a closed-loop system for adjusting the chemical-mechanical polishing tool process parameters. The non-intrusive measurement system consists of an interferometer measurement technique utilizing ultrasound or electromagnetic radiation transmitters and receivers aligned to cover any portion of the radial length of a polishing pad surface. The measurement system is sensitive to relative changes in pad thickness for uniformity, and to abrupt changes such as detecting wafer detachment from the CMP wafer carrier.

Method and apparatus of monitoring polishing pad wear during processing

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Yorktown Heights, NY, United States of America

Mark A Jaso