Advanced Micro Devices Corporation

International Computers Limited

Legerity, Inc.

Mark A Ireton

John G Bartkowiak

Saf M Asghar

Safdar M Asghar

Costas S Xydeas

Thomas W Lynch

Gerald D Champagne

Christopher J Yard

Andrew Mills

Corbett A Marler

Dimitris Hiotakakos

A microprocessor including an instruction translation unit and a storage control unit is provided. The instruction translation unit scans the instructions to be executed by the microprocessor. The instructions are coded in the instruction set of a CPU core included within the microprocessor. The instruction translation unit detects code sequences which may be more efficiently executed in a DSP core included within the microprocessor, and translates detected code sequences into one or more DSP instructions. The instruction translation unit conveys the translated code sequences to a storage control unit. The storage control unit stores the code sequences along with the address of the original code sequences. As instructions are fetched, the storage control unit is searched. If a translated code sequence is stored for the instructions being fetched, the translated code sequence is substituted for the code sequence.

Microprocessor configured to translate instructions from one instruction set to another, and to store the translated instructions

An execute unit including an integer operation circuit is provided. The integer operation circuit is dynamically configurable to operate upon many different widths of operands. A single pair of operands may be operated upon, wherein the width of the operands is the maximum width the integer operation circuit is configured to handle. Alternatively, multiple pairs of operands having narrower widths may be operated upon. The instruction being executed defines the width of the operands and therefore the number of operands. Wide operand operations are performed at a rate of one per instruction, and a rate of more than one instruction is achieved for narrow operands. The same integer operation circuitry is employed to perform both narrow and wide integer operations. Silicon area consumed by the integer operation circuitry may be reduced as compared to a wide integer operation circuit and multiple narrow integer operation circuits.

Execute unit configured to selectably interpret an operand as multiple

The present invention comprises an improved vocoder system and method for estimating the pitch of a speech signal. The speech signal comprises a stream of digitized speech samples. The speech samples are partitioned into frames. For each frame of the speech signal, an optimal order-two inverse filter is determined. The optimal order-two inverse filter is determined by computing an order-two inverse filter at various locations within the speech frame. For each order-two inverse filter an energy value is calculated which represents the proportion of energy which would remain if the speech signal were filtered with the order-two inverse filter. The order-two inverse filter which minimizes the energy proportion is chosen to be the optimal order-two inverse filter. The optimal order-two inverse filter is then used to filter the samples of the speech frame. An autocorrelation is performed on the filtered signal for a range of tine-delay values. The peaks of the autocorrelation function are analyzed to determine the pitch period.

System and method for determining a first formant analysis filter and

A vocoder system and method for estimating the pitch of a speech signal. The speech signal comprises a stream of digitized speech samples. The speech samples are partitioned into frames. For each frame of the speech signal, the following processing steps are performed. First, an optimal order-two inverse filter is determined based on the samples of the speech frame. Second, a dominant formant frequency is calculated from the coefficients of the optimal order-two inverse filter. Third, an autocorrelation function is calculated on the samples of the speech frame. The autocorrelation is performed for a range of time-delay values over which the pitch period and its multiples might be expected to occur. Fourth, the peaks of the autocorrelation function are analyzed incorporating the knowledge of the dominant formant period (which is the inverse of the dominant formant frequency). Normally, the dominant formant is the first formant. Thus, the dominant formant period defines the expected time-delay for the first formant peak in the autocorrelation function. As such, any peak in the autocorrelation function occurring with a time-delay equal to the dominant formant period is treated with increased caution before being accepted as the pitch period.

First formant location determination and removal from speech correlation

A digital voice data storage and retrieval system using a low bit rate encoder which provides enhanced speech signal quality while also reducing memory size requirements. The system comprises a voice coder/decoder which preferably includes a digital signal processor (DSP) and also preferably includes a local memory. During encoding of the voice data, the voice coder/decoder receives voice input waveforms and generates a parametric representation of the voice data. A storage memory is coupled to the voice coder/decoder for storing the parametric data. During decoding of the voice data, the voice coder/decoder receives the parametric data from the storage memory and reproduces the voice waveforms. According to the invention, an interframe smoothing method is performed on the parametric data after encoding of all of the speech data has completed and the parametric data has been stored in the storage memory. The interframe smoothing is performed either in the background after the coding process has completed or in real time during the decoding process immediately prior to converting the parametric data back to signal waveforms. Since all of the voice input data has already been converted to parametric data and stored in memory, parametric data from a virtually unlimited number of prior and successive frames is available for use by the smoothing algorithm. Therefore, the present invention provides more accurate smoothing and provides enhanced speech signal quality over prior systems.

System and method for enhanced speech quality in voice storage and

The system and method of the present invention uses a zero-crossing rate measurement in order to determine the initiation and/or termination of speech in an audio signal input. It is especially well suited for detecting the termination of a telephone message in a telephone answering device. Specifically, a sample of the zero-crossing rate signal is determined by counting the number of consecutive speech samples required for the occurrence of a pre-defined number of consecutive zero-crossings. The resultant zero-crossing rate signal is smoothed and applied to a differentiator. A short-time magnitude integration is performed to measure the energy in the differentiated signal. The output of the magnitude integration is provided to a threshold detector which produces a sequence of decision values indicating the presence or absence of speech. Finally, the decision values are filtered to produce a more definitive sequence of final decision values.

Detection of tonal signals

An improved vocoder system and method for estimating pitch in a speech waveform which pre-filters speech data with improved efficiency and reduced computational requirements. The vocoder system is preferably a low bit rate speech coder which analyzes a plurality of frames of speech data in parallel. Once the LPC filter coefficients and the pitch for a first frame have been calculated, the vocoder then looks ahead to the next frame to estimate the pitch, i.e., to estimate the pitch of the next frame. In the preferred embodiment of the invention, the vocoder filters speech data in a second frame using a plurality of the coefficients from a first frame as a multi pole analysis filter. These coefficients are used as a 'crude' two pole analysis filter. The vocoder preferably includes a first processor which performs coefficient calculations for the second frame, and a second processor which performs pre-filtering and pitch estimation, wherein the second processor operates substantially simultaneously with the first processor. Thus, the vocoder system uses LPC coefficients for a first frame as a 'crude' multi pole analysis filter for a subsequent frame of data, thereby performing pre-filtering on a frame without requiring previous coefficient calculations for that frame. This allows pre-filtered pitch estimation and LPC coefficient calculations to be performed in parallel. This provides a more efficient pitch estimation, thus enhancing vocoder performance.

System and method for improved pitch estimation which performs first

A system and method for performing software patches for embedded system devices in which the firmware of the system is included in non-alterable storage of the device. The patch mechanism provides a means for finding firmware errors, prototyping fixes to the errors and/or prototyping new functionality of the firmware of the embedded system. The system comprises an embedded system device coupled to an external memory. The device includes a non-alterable memory, including firmware, coupled to a processor. The device further includes a relatively small amount of patch RAM within the device also coupled to the processor. The patches are loaded from the external memory into the patch RAM. The device further includes a means for determining if one or more patches are to be applied. If the device detects a patch to be applied, the system loads the patch from the external memory into the patch RAM. The device also includes a breakpoint register. When the value of the program counter of the processor equals the value in the breakpoint register, a patch insertion occurs, i.e., the processor deviates from executing firmware to executing patch instructions. Preferably, the embedded system device comprises a single integrated circuit. The processor may include a plurality of breakpoint registers. The patch may be encrypted for increased security. Multiple patches may be chained together, and run-time patch replacement is contemplated.

System and method for performing software patches in embedded systems

A method of managing a memory array having a plurality of erasable sectors. The method initially assigns at least one of the erasable sectors as a storage array and at least one of the erasable sectors as an update array. At least one data file is then sequentially written into the storage array beginning at a starting byte within the storage array. Each data file written into the storage array is initially designated as an active file. Thereafter, one or more of the active files is deleted by re-designating an active file as a deleted file. The deletion of active files is accomplished without erasing any of the erasable sectors. In a presently preferred embodiment, the deletion of files is accomplished by setting an Active/Delete flag in a header of the file. After deleting one or more active files, the array comprises at least one active file and at least one deleted file. Thereafter, the array is periodically updated by copying the active files from the storage array to the update array and erasing the sectors that comprise the storage array.

Simplified file management scheme for flash memory

An instruction translation unit is provided which reduces instructions from a source instruction set to a set of intermediate, atomic operations. The atomic operations are then recombined into instructions in the target instruction set. An execution core coupled to the instruction translation unit may be configured to execute instructions from the target instruction set. However, compatibility with the source instruction set is maintained. By reducing a plurality of source instructions into atomic operations, portions of multiple source instructions may be combined into a target instructions. The execution core may thereby be more efficiently utilized.

Instruction translation unit configured to translate from a first

A vocoder for generating speech from a plurality of stored speech parameters which efficiently computes a band limited noise signal for use in the speech production model. The band limited noise signal generator includes a white Gaussian noise generator coupled to a band-width limiting filter. The resulting band limited white Gaussian noise signal is provided to a bank of modulators, each having predetermined modulation frequency. The outputs of each of the modulators are provided to variable gain units and summed together to produce the band limited noise signal.

System and method for generating re-configurable band limited noise

A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

CPU with DSP having function preprocessor that converts instruction

A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, an also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

Central processing unit including a DSP function preprocessor which

A microprocessor is provided which detects dependencies among instructions. The microprocessor assigns each instruction to a processing element or elements which perform the operation specified by the instruction. Additionally, the microprocessor is configured to dynamically alter the interconnect between the processing elements such that dependent operations receive operands from the operations upon which they depend. In particular, an instruction which computes a result upon which another instruction depends is connected to provide the result to that instruction. Routing of data between processing elements is determined prior to the execution of the instructions. Using the dynamic reconfiguration of interconnections, the microprocessor executes instruction sequences more efficiently than a DSP which is optimized for another instruction sequence. Because the connections are reconfigurable, the microprocessor may be configured for the efficient execution of many different instruction sequences (as opposed to the limited number imposed by typical DSPs).

Microprocessor configured to dynamically connect processing elements

A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X8 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a look-up table which stores instruction sequences which implement DSP functions. Each pattern in the look-up table is compared with an instruction sequence to determine if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the DSP function preprocessor converts the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core. Thus, the DSP offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSPs. Thus the present invention is backwards compatible with existing software.

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Austin, TX, United States of America

Mark A Ireton