Rambus Inc.

Leland Stanford Junior University

Other

Renesas Electronics Corporation

Facebook Technologies, LLC

Mark A Horowitz

Jared L Zerbe

Michael P Farmwald

Kevin S Donnelly

Craig Edward Hampel

Bruno Werner Garlepp

Richard Maurice Barth

Vladimir Marko Stojanovic

Frederick Abbott Ware

Anthony G Bessios

Alfredo Moncayo

Stefanos Sidiropoulos

Donald C Stark

Elad Alon

Fred F Chen

Pak Shing Chau

Jun Y Kim

Ely K Tsern

Yi-Ren Ng

Leung Yu

Patrick M Hanrahan

Carl William Werner

Marc Stewart Levoy

Grace Tsang

Jason C Wei

Andrew C C Ho

Roxanne T Vu

Tsyr-Chyang Ho

Benedict Chung-Kwong Lau

Andrew P Ho

Haw-Jyh Liaw

Andrew C Ho

James A Gasbarro

Billy Wayne Garrett, Jr

Matthew Murdy Griffin

Wingyu Leung

Scott C Best

Thomas H Lee

Xingchao C Yuan

Yiu-Fai Chan

Brian S Leibowitz

Brent Steven Haukness

Benedict C Lau

Hae-Chang Lee

Jade M Kizer

Mark G Johnson

John Bradly Dillon

Gary Bela Bronner

Chanh Vi Tran

Joseph Mardell Kahn

Thomas H Greer, Iii

Marc A Levoy

Amir Amirkhany

Shanhui Fan

Olav Solgaard

Nhat M Nguyen

William Franklin Stonecypher

Fariborz Assaderaghi

Mark D Kellam

Xiangchao Yuan

Steven Cameron Woo

Kun-Yung Chang

Donald Victor Perino

Jaeha Kim

Nancy David Dillon, Legal Representative

Dennis Kim

Winston K Lee

John Philip Privitera

Ian P Shaeffer

Noy Cohen

Yingxuan Li

Edward Buckley

Aliazam Abbasfar

Ofer Shacham

Neel Suresh Joshi

Ramin Farjad-Rad

William Thomas Blank

Ilias Pappas

Craig Steven Levin

Paul Michael Farmwald

Clemenz L Portmann

Wendemagegnehu Beyene

Rehan Hameed

Wajahat Qadeer

Kevin D Jones

Samuel J Yang

Stephen Richardson

Toshitsugu Kawashima

Nancy David Dillon

Logan Grosenick

John George Maneatis

Bennett Sampson Wilburn

Aaron S Andalman

Michael J Broxton

By Nancy David Dillon

Karl A Disseroth

Marc C Levoy

Christoforos Kozyrakis

Frances W Y Lau

Hwang Ho Choi

A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Memory controller with error detection and retry modes of operation

Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

Self-annealing data storage system

Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

System including hierarchical memory modules having different types of integrated circuit memory devices

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

High speed signaling system with adaptive transmit pre-emphasis

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

Partial response receiver

Dynamic memory rank configuration

Disclosed herein are display systems and techniques for operating a display in a display system. An output image is formed by scanning a column of light emitters such that emitters in different rows of the column contribute to a same location in the output image. The emitters are driven using pulse-width modulation (PWM). PWM pulses are applied in synchronization with the scanning to cause emitters to emit light at an intensity corresponding to an illumination parameter. The driving includes generating, based on an illumination parameter, a PWM pulse by applying an analog signal in combination with applying a digital signal. The analog signal controls an amplitude of the PWM pulse. The digital signal controls a duration of the PWM pulse.

Display systems with hybrid emitter circuits

A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Technique for determining performance characteristics of electronic devices and systems

Growing community of inventors

Menlo Park, CA, United States of America

Mark A Horowitz