Intel Corporation

Mark A Holler

Simon M Tam

Hernan Adolfo Castro

Been-Jon K Woo

Sandra S Lee

Paul Thomas Buchheit

George J Korsh

George Perlegos

Aaron M Tsirkel

Paolo Gargini

Ender Hokelek

Michael Allen Van Buskirk

Gary R Bradski

Alan H Kramer

Chin S Park

Umberto Santoni

George R Canepa

Ronald G Benson

Ryan A Boller

Kenneth R Buckmann

Siang-Chun The

Jay M Diamond

Ender Hokeler

A computer is power managed by detecting the presence of a user. A camera is associated with the computer and the output from the camera is analyzed to determine if the user is present. If the user is present, then the computer is maintained in its non-power manage state. When the user leaves, however, the user's presence is no longer detected by the camera, and the power managed state can be quickly entered.

Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time

A computer is power managed by detecting the presence of a user. A camera is associated with the computer and the output from the camera is analyzed to determine if the user is present. If the user is present, then the computer is maintained in its non-power manage state. When the user leaves, however, the user's presence is no longer detected by the camera,and the power managed state can be quickly entered.

According to one embodiment of the invention, an apparatus is provided that includes a projection screen located on a wall of a workspace. The apparatus also includes a frontal-view camera located behind the projection screen. The frontal view camera captures a frontal-view image of the workspace through a hole in the projection screen. Additionally, the apparatus includes a projector to project an image of an individual outside the workspace onto the projection screen, such that the hole is located within a face of the image of the individual.

Office workspace having a multi-surface projection and a multi-camera system

The generation of control variables for computer vision is disclosed. In one embodiment of the invention, a computerized system includes a video camera and a controller. The video camera tracks an object, such as the head of a user of the computer. The controller generates control variables having sensitivity to movement of the object that varies in accordance with movement of the object from a neutral position.

Computer vision control variable transformation

An adaptive distance calculating neural network classifier chip accepts high dimensionality input pattern vectors with up to 256 5-bit elements per vector and compares the input vector with up to 1024 prototype vectors stored on-chip by calculating the distance between the input vector and each of the prototype vectors. The classifier further provides for identifying up to 64 classes to which the prototype vectors belong. If the distance between input and prototype vector is less than a programmable threshold distance, the prototype fires and the class to which it belongs is identified. If prototype vectors belonging to more than one class fire, a probabilistic model based on Parzen windows may be invoked to resolve the classification by providing the relative probabilities of various class membership. The classifier chip is trainable by supplying appropriate training vectors and associated class membership. Distance and probability parameters are generated during training and are stored for use in the classification mode. Incremental training is also provided so that additional prototypes may be added to an existing base. In order to extend the classifier capacity, multichip operation is provided under the supervision of a system administrator controller/CPU.

Distance calculating neural network classifier chip and system

A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed. Next, the network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.

Method of increasing the accuracy of an analog circuit employing

A difference calculating neural network is disclosed having an array of synapse cells arranged in rows and columns along pairs of row and column lines. The cells include a pair of floating gate devices which have their control gates coupled to receive one of a pair of complementary input voltages. The floating gate devices also have complementary threshold voltages such that packets of charge are produced from the synapse cells that are proportional to the difference between the input and voltage threshold. The charge packets are accumulated by the pairs of column lines in the array.

Difference calculating neural network utilizing switched capacitors

In an apparatus for multiplexed operation of multi-cell neural network, the reference vector component values are stored as differential values in pairs of floating gate transistors. A long-tail pair differential transconductance multiplier is synthesized by selectively using the floating gate transistor pairs as the current source. Appropriate transistor pairs are multiplexed into the network for forming a differential output current representative of the product of the input vector component applied to the differential input and the stored reference vector component stored in the multiplexed transistor pair that is switched into the multiplier network to function as the differential current source. Pipelining and output multiplexing is also described in other preferred embodiments for increasing the effective output bandwidth of the network.

Neural network with multiplexed snyaptic processing

A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed. Next, network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.

Method of increasing the accuracy of an analog neural network and the

A multi-layer electrically trainable analog neural network employing multiplexed output neurons having inputs organized into two groups, external and recurrent (i.e., feedback). Each layer of the network comprises a matrix of synapse cells which implement a matrix multiplication between an input vector and a weight matrix. In normal operation, an external input vector coupled to the first synaptic array generates a Sigmoid response at the output of a set of neurons. This output is then fed back to the next and subsequent layers of the network as a recurrent input vector. The output of second layer processing is generated by the same neurons used in first layer processing. Thus, the neural network of the present invention can handle N-layer operation by using recurrent connections and a single set of multiplexed output neurons.

Multi-layer neural network employing multiplexed output neurons

A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase region is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.

Method for improving erase characteristics of buried bit line flash

A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown without the use of a sacrificial-oxide growth and removal method. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase regon is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.

An analog neural network is described which provides a means for reducing the sensitivity of the network to temperature and power supply variations. A first circuit is utilized for generating a signal which exhibits a dependence on temperature corresponding to the variation normally experienced by the network in response to a change in temperature. A second circuit is employed to generate another signal which exhibits a similar dependence, except on power supply variations. By coupling these signals as inputs to the neural network the sensitivity of the network to temperature and power supply fluctuations is essentially nulified.

Neural network exhibiting improved tolerance to temperature and power

A cell employing floating gate storage device particularly suited for neural networks. The floating gate from the floating gate device extends to and becomes part of a second, field effect device. Current through the second device is affected by the charge on the floating gate. The weighting factor for the cell is determined by the amount of charge on the floating gate. By charging the floating gate to various levels, a continuum of weighting factors is obtained. Multiplication is obtained since the current through the second device is a function of the weighting factor.

Semiconductor cell for neural network and the like

The present invention covers a synapse cell for providing a weighted connection between a differential input voltage and a single output summing line having an associated capacitance. The connection is made using one or more floating-gate transistors which provide both excitatory as well as inhibitory connections. As configured, each transistor's drain is coupled to an input line and its source is coupled to the output summing line. The floating-gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a voltage pulse having a certain duration is applied to the control gate of the floating-gate transistor, a current is generated which acts to discharge the capacitance associated with the output summing line. The current is directly proportional to the charge stored on the floating-gate member and the duration of the input pulse.

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Palo Alto, CA, United States of America

Mark A Holler