Hewlett-packard Company

Mark A Forsyth

Eric R Delano

Patrick Knebel

Eric R DeLano

Craig A Gleason

A computer system implementing two levels of translation lookaside buffers (TLBs). The first-level TLBs are small, two-set associative, have a short access time and reside on the CPU chip. The second-level TLBs, on the other hand, are large, direct mapped, and reside in otherwise unused portions of the cache tag RAMs of the instruction and data cache sub-systems. As a result of this arrangement, performance may be improved without limiting the amount of available cache memory for a given implementation. Even if higher capacity memory devices are required for implementing the second-level TLBs in the cache tag RAMs in accordance with the invention, a significant savings over the cost of two sets of smaller devices would still result.

Two-level TLB having the second level TLB implemented in cache tag RAMs

A computer system having a central processor unit (CPU) with a reduced instruction set, a decoder and a data cache memory, for processing an instruction to retrieve data from a main memory to prevent a data cache miss. The system decodes an instruction requiring the CPU to load a value into a read only general purpose memory register, the instruction thereby indicating to the CPU to perform a prefetch operation and providing information corresponding to an address of the data to be fetched from the main memory. The system processes, substantially simultaneously, further instructions following the load register instruction and the prefetch operation by determining the address in main memory of the data to be prefetched using the information provided by the load instruction, fetching the data from the main memory, and storing the data in the data cache memory to permit accesses to the data and thereby reduce the penalty associated with a data cache miss.

System and method for reducing the penalty associated with data cache

A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the cache memory unit, produces the predecode bits for utilization by a superscalar processor. The circuitry of the predecode unit is comprised of logic and latches. The predecode unit includes two main paths for transporting instruction information: a predecode path and an instruction path. The instruction path buffers instructions sent from memory to cache as information from these instructions are decoded in the predecode path. The predecode path includes a decoder and a bit information unit. The decoder identifies the instruction type by monitoring the op-code of instructions entering the predecode unit. The bit information unit is coupled to the decoder and receives signals indicating instruction type and passes these signals through logic gates to obtain whether instructions can be bundled. The bit information unit then transfers to cache bundle signals and instruction type signals. These signals are stored as predecode bits along with instructions from the instruction path in the cache.

Predecoding instructions for supercalar dependency indicating

A hardware mechanism capable of performing state saving and restoring operations, for use in a computer environment having a computer system having a central processor unit (CPU) with one or more data buses, a set of general purpose registers, instruction decoding logic and a mechanism for detecting interrupt conditions. The present invention generates new SAVE and RESTORE control signals and additional memory elements temporarily store the contents of the general purpose registers during interrupt conditions. The hardware mechanism includes an input section for transferring information from the one or more data buses to general purpose registers for storing the information. An output section is used for transferring the stored information from the general purpose registers to the data bus(es). A set of shadow latches store the contents of the general purpose registers when the CPU issues the SAVE control signal and transfer the contents back to the general purpose registers when the CPU issues the RESTORE control signal.

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Fort Collins, CO, United States of America

Mark A Forsyth