Freescale Semiconductor,inc.

Motorola Corporation

Everspin Technologies, Inc.

Mark A Durlam

Saied N Tehrani

Eugene Youjun Chen

Gregory W Grynkewich

Kelly Wayne Kyler

Brian R Butcher

Clarence J Tracy

Mark DeHerrera

Gloria J Kerszykowski

Jon Michael Slaughter

Robert W Baird

Young Sir Chung

Xiaodong T Zhu

Thomas Andre

Nicholas David Rizzo

Jaynal Abedin Molla

Joseph J Nahas

Bradley J Garni

Eric John Salter

Mark F Deherrera

J Jack Ren

Bradley Neal Engel

Peter K Naji

Theodore Zhu

Loren J Wise

Richard Williams

Thomas V Meixner

Chitra K Subramanian

Kenneth H Smith

John J D'Urso

Jenn-Hwa Huang

Marino J Martinez

Jeffrey H Baker

Earl D Fuchs

Charles A Synder

Ernie Schirmann

Mitchell T Lien

Jiang-kai Zuo

Herbert Goronkin

William J Ooms

Jonathan K Abrokwah

Ronald N Legge

Renu Whig Dave

X Theodore Zhu

Steven M Smith

Jaeshin Cho

Jing Shi

Wayne A Cronin

Charles W Snyder

Clarance J Tracy

Li Hsin Chang

Michael J Roll

A memory device, such an MRAM device, includes self-healing reference bits () associated with a set of array bits (). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits () is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit () is toggled back to its original state.

Methods and apparatus for a memory device with self-healing reference bits

An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction ('MTJ') temperature sensor disposed over the heat source.

Magnetic tunnel junction temperature sensors

Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction ('MTJ') temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.

Magnetic tunnel junction temperature sensors and methods

A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices

A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.

Method of manufacturing a magnetoelectronic device

An integrated circuit device includes a magnetic random access memory ('MRAM') architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

MRAM embedded smart power integrated circuits

A method for fabricating a flux concentrating system () for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line () formed in a substrate () and forming a first material layer () overlying the bit line () and the substrate (). Etching is performed to form a trench () in the first material layer () and a cladding layer () is deposited in the trench (). A buffer material layer () is formed overlying the cladding layer () and a portion of the buffer material layer () and a portion of the cladding layer () is removed.

Method for fabricating a flux concentrating system for use in a magnetoelectronics device

Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction ('MTJ') core disposed between a first conductive layer and a second conductive layer. The MTJ core can be used to sense the first current and produce a second current based on the first current sensed at the MTJ core.

Methods of implementing magnetic tunnel junction current sensors

An integrated circuit device () comprises a substrate () and MRAM architecture () formed on the substrate (). The MRAM architecture () includes a MRAM circuit () formed on the substrate (); and a MRAM cell () coupled to and formed above the MRAM circuit (). Additionally a passive device () is formed in conjunction with the MRAM cell (). The passive device () can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture () and the passive device () facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (), resulting in three-dimensional integration.

Passive elements in MRAM embedded integrated circuits

An integrated circuit device includes a magnetic random access memory ('MRAM') architecture and at least one inductance element formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture and the inductance element facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

3-D inductor and transformer devices in MRAM embedded integrated circuits

An integrated circuit device includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may includes a Magnetic Tunnel Junction ('MTJ') core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

Magnetic tunnel junction current sensors

Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.

Magnetoresistive random access memory devices and methods for fabricating the same

A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

MRAM architecture with electrically isolated read and write circuitry

Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

Magnetoresistive random access memory device structures and methods for fabricating the same

A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().

Cladded conductor for use in a magnetoelectronics device and method for fabricating the same

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Chandler, AZ, United States of America

Mark A Durlam