Intel Corporation

Lucent Technologies Inc.

Agere Systems Inc.

Mark A Bordogna

Janardhan H Satyanarayana

Yoni Landau

Joseph Elide Landry

Philip Sidney Dietz

Warren Clifton Trested, Jr

Jeffrey Robert Towne

Assaf Benhamou

Jonathan A Robinson

Robert G Southworth

Adam Benjamin Healey

Mark H Davis

Mika Nystroem

Kurt Arnold Hedlund

Srinivasan S Iyengar

Larry N Wakeman

Gary Lynn McElvany

Diwakar Suvvari

Janus Biegaj

Ramamurthy Krithivas

Robert J Munoz

Ralf Dohmen

Sita Rama Chandrasekhar Mallela

Christopher W Hamilton

James E Ballintine

James Mark Sepko

Wilhelm Kremer

Juergen Beck

Wolfram Sturm

Sundararajan Cidambara

Peter A Stropparo

Dominic Dominijani

Dominic Dominijanni

Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

Timestamp alignment across multiple computing nodes

Methods and apparatus for data plane control of network time sync protocol in multi-host systems. A network interface controller (NIC) is configured to implement a network data plane that is associated with a software-based control plane implemented in the multi-host system. The NIC includes a primary timer and secondary timers at distributed endpoints such as network ports. The NIC receives network time packets having network timestamps and employs a secondary timer to associate a local timestamp with the packets. The network and local timestamps are compared by a network intellectual property block (network IP) in the data plane datapath to adjust the primary and secondary timer(s) to match the network time. The network IP uses a 2-bit wire protocol to increment and/or decrement the primary and secondary timer(s) that enables the timers to be adjusted with a nanosecond granularity.

Method and apparatus for data plane control of network time sync protocol in multi-host systems

Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.

Timestamp alignment for multiple nodes

Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

Technologies for timestamping with error correction

In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.

High accuracy time stamping for multi-lane ports

Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.

Technologies for high-precision timestamping of packets

Electronic devices coupled to a network may exchange messages containing time-of-day information synchronization of the internal clocks. The information exchanged may include the instant at which a message leaves the electronic device. Discussed herein are methods and systems that allow 1-step timestamping of messages containing time-of-day information. The 1-step timestamping methods and systems may reduce the impact of non-deterministic time delays in the transmit path (e.g., encryption, expansion, inclusion of tags), and may improve the accuracy of the time-of-day information of the packets. For example, systems and methods may allow accurate 1-step timestamping of IEEE 1588 Precision Time Protocol packets with the uncertainty of delays from MACSec encryption or other security mechanisms. Some embodiments employ estimation non-deterministic delay of previously transmitted packets to estimate the state of the transmit path. Some embodiments include communication channels to allow circuitry in transmit path to report the state.

One-step time stamping of synchronization packets for networked devices

Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.

Protected real time clock with hardware interconnects

Described embodiments provide for a reassembly system for processing an asynchronous transfer mode (ATM) cell of data into an ATM adaptation layer (AAL) packet. A preprocessor module identifies a first conversation identification of one or more minipackets in the ATM cell, and reassembles the one or more minipackets having the first conversation identification into a portion of the AAL packet. A preprocessor determines if a trigger has occurred. In response to a trigger, the preprocessor sends a portion of the reassembled minipackets having the first conversation identification to a destination processor.

Packet reassembly processing

Methods and apparatus are provided for circuit emulation services over cell and packet networks. A constant bit rate traffic stream is mapped to one of a cell and packet structure. The constant bit rate traffic stream is mapped to one or more cells and the one or more cells are selectively translated to one or more packets if a packet stream is selected. In addition, one of a received cell and packet stream are mapped to a constant bit rate traffic stream. The packet stream is selectively translated to one or more cells and the one or more cells are translated to the constant bit rate traffic stream. A clock can optionally be recovered from the received cell or packet stream.

Method and apparatus for circuit emulation services over cell and packet networks

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Andover, MA, United States of America

Mark A Bordogna