Intel Corporation

Mark A Beiley

Lawrence T Clark

Eric J Hoffman

James E Breisch

Edward John Bawolek

Kevin M Connolly

Akira Kakizawa

Cory E Weber

Shaofeng Yu

Zong-Fu Li

Jung S Kang

Berni W Landau

Joseph W Parks, Jr

Jon M Dhuse

Morteza Cyrus Afghahi

Luke A Johnson

Rajendran Nair

Mamun Ur Rashid

Bart R McDaniel

Mahesh J Deshmane

According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.

Slew rate control mechanism

A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.

Test circuit for delay lock loops

A circuit includes a capacitor formed with a dielectric including the dielectric encasing elements of the circuit. A detector detects changes in the capacitance of the capacitor.

Method and apparatus to detect circuit tampering

A method and apparatus for employing a light shield to modulate pixel color responsivity. The improved pixel includes a substrate having a photodiode with a light receiving area. A color filter array material of a first color is disposed above the substrate. The pixel has a first relative responsivity. A light shield is disposed above the substrate to modulate the pixel color responsivity. The light shield forms an aperture whose area is substantially equal to the light receiving area adjusted by a reduction factor. The reduction factor is the result of an arithmetic operation between the first relative responsivity and a second relative responsivity, associated with a second pixel of a second color.

Method and apparatus for employing a light shield to modulate pixel color responsivity

A mechanism is provided for delivering power to an on-die component (such as a buffer circuit). This may include a package unit having a low frequency delivery path and a high frequency delivery path and a die having the on-die component and a capacitive device each coupled in parallel between a first node and a second node. The die may further include a low frequency reception path and a high frequency reception path. The low frequency reception path may couple to the low frequency delivery path on the package unit and to the first node. The high frequency reception path may couple to the high frequency delivery path on the package unit and to the first node. The high frequency reception path may include a damping resistor.

Multi-frequency power delivery system

In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.

Method and apparatus for increasing retention time in image sensors having an electronic shutter

What is disclosed is an apparatus for reducing row reset noise in photodiode based complementary metal oxide (CMOS) sensors. The apparatus uses at least one reference pixel for each row of pixels in a sensor array. Also, a reset noise elimination unit is provided to adjust the values received from the pixels in a particular row by an adjustment value determined from the reset values received from the reference pixels. Additionally, a method of using the apparatus is disclosed. The method has a step of providing a first reset signal to a row of pixels including the reference pixels. The method also reads out a first set of values from this row after integration. The method continues with providing a second reset signal to the row and a second set of values is read from the row. An adjustment value is calculated from the difference of the values which are read out from the reference pixels.

Imaging system having a sensor array reset noise reduction mechanism

An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.

Method and apparatus for self-calibration and fixed-pattern noise removal in imager integrated circuits

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

Reduced leakage trench isolation

A semiconductor circuit having an analog storage array, a sense amplifier array in which each sense amp cell generates a differential signal pair in response to receiving first and second signals from the storage array. The circuit also includes an analog multiplexer through which a selected differential signal pair is driven into a signal processing pipe. In another embodiment, the sense amp cells each include an operational amplifier (opamp) pair configured as unity-gain closed loop amplifiers for driving the differential signal pair through the analog multiplexer. To improve settling time, the opamps are designed to provide an underdamped response while loaded with the analog transmission path through the analog mux. In yet another embodiment, each sense amp cell is activated one clock cycle before it is read. This allows speedy readout while transitioning from one cell to the next. Also, maintaining only two cells active at any given time during readout helps reduce power dissipation and substantially decouples power dissipation in the sense amp array from the size of the array. The embodiments of the invention can be used in different types of imaging systems, including for instance a digital camera.

High speed readout architecture for analog storage arrays

A circuit includes a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors.

Method and apparatus to produce a random bit sequence

A method for controlling a sensor to reduce reset noise is disclosed. The method including the steps of providing a reset command including a RESET signal and a first SAMPLE signal. The method also includes the steps of providing a read command including a first ADDRESS signal, a second SAMPLE signal, and a second ADDRESS signal. An apparatus including a system controller and a sensor controlled by the system controller is also disclosed. In one embodiment, the method and apparatus is provided for a sensor in a sensor array that is read-out in a pipelined fashion.

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Chandler, AZ, United States of America

Mark A Beiley