Xilinx, Inc.

Dolby Laboratories Licensing Corporation

Mark A Alexander

Alan Jeffrey Seefeldt

Dirk Jeroen Breebaart

C Phillip Brown

Joshua Brandon Lando

Chunjian Li

Robert O Conn

Steven J Carey

Sean A Koontz

Austin H Lesea

Peter H Alfke

Paul Ying-Fung Wu

Romi Mayder

Austin S Tavares

Howard Johnson

Media input audio data corresponding to a media stream and microphone input audio data from at least one microphone may be received. A first level of at least one of a plurality of frequency bands of the media input audio data, as well as a second level of at least one of a plurality of frequency bands of the microphone input audio data, may be determined. Media output audio data and microphone output audio data may be produced by adjusting levels of one or more of the first and second plurality of frequency bands based on the perceived loudness of the microphone input audio data, of the microphone output audio data, of the media output audio data and the media input audio data. One or more processes may be modified upon receipt of a mode-switching indication.

Media-compensated pass-through and mode-switching

Integrated circuits are fabricated with mounted discrete capacitors. Bond pads and land pads are fabricated on a semiconductor wafer. Discrete capacitors are mounted on the semiconductor wafer with flexible adhesive. The flexible adhesive accommodates a difference in thermal expansion between the discrete capacitors and the semiconductor wafer. The land pads are electrically coupled to the electrodes of the discrete capacitors. The semiconductor wafer is separated into multiple semiconductor dice. The semiconductor dice are mounted in respective packages. The bond pads on each semiconductor die are electrically coupled to the interconnect terminals of the respective package.

Integrated circuit having a discrete capacitor mounted on a semiconductor die

Approaches for analyzing a power grid of an integrated circuit are described. In one embodiment, a method includes selecting at least one portion of the integrated circuit to be analyzed. A power grid model corresponding to the integrated circuit is retrieved from a database, and a first simulation of the programmable integrated circuit is performed. The first simulation generates a respective waveform of an electrical characteristic over time for each connection of a component within the selected portion to voltage supply or voltage ground. A simulation is performed of the power grid model using the respective waveforms as input stimulus for each connection in the selected portion.

Simulation of integrated circuit power grid networks

Predicting simultaneous switching output noise of an IC device is described. User input is obtained. The user input includes: an identification of an input/output bank of an integrated circuit die; an identification of a device package substrate to which the integrated circuit die is to be attached; and an identification of input/output interface to be used by the input/output bank. A noise factor and an impedance are selected responsive to the user input. The noise factor is multiplied with the impedance to provide a result. The result, which is output, is a prediction of the simultaneous switching output noise of the integrated circuit device.

Predicting simultaneous switching output noise of an integrated circuit

The relative timing of triggering switching events in a circuit block of an IC device is dynamically adjusted in response to fluctuations in device's supply voltage to minimize clock jitter caused by supply voltage noise. A control circuit monitors supply voltage fluctuations, and in response thereto dynamically phase-shifts a clock signal that triggers the switching events so that the switching events occur during relatively quiet time intervals in which fluctuations in the supply voltage are minimal.

Clock auto-phasing for reduced jitter

A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affected by the electrical disturbances. Next, principles of superposition are utilized to coherently combine each of the electrical disturbance waveforms in the time domain to generate the predicted SSO noise waveform that is imposed upon the affected signal conduction path. The electrical disturbance waveforms may be produced either by using bench measurements performed on an actual integrated circuit, by simulation, or by a combination of simulation and bench measurements.

Method for predicting simultaneous switching output (SSO) noise

Induced crosstalk is predicted for the input/output pins of a programmable logic device. Signal edge rates for the input/output pin are determined from selected interface protocols for the input/output pins. For each pair of the input/output pins, a first coupling coefficient specifies a coupling between the pair of input/output pins within a package for mounting the programmable logic device to a printed circuit board. A depth is input for each via coupled to an input/output pin by the printed circuit board. From the via depths, a second coupling coefficient is determined for each pair of the input/output pins that satisfy a separation criterion. For each of the input/output pins, a predicted value of an induced crosstalk is determined from the first and second coupling coefficients for each pair that includes the input/output pin and another input/output pin, and from the signal edge rate of this other input/output pin.

Predicting induced crosstalk for the pins of a programmable logic device

An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down ('de-tune') data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.

Reducing noise on a supply voltage in an integrated circuit

A packaged integrated circuit ('IC') includes a substrate, an IC die, and a molded plastic lid. A test point standoff is electrically connected to the IC die and extends away from the surface of the package substrate through the molded plastic lid toward the top surface of the molded plastic lid. The top of the test point standoff is below the top surface of the molded plastic lid.

Packaged integrated circuit with raised test points

A packaged semiconductor device uses built-in self test to characterize voltage between points within the semiconductor die during a current discontinuity generated in the semiconductor die. The semiconductor die is operated to generate a current discontinuity, or several sequential current discontinuities, and the voltage is measured with an on-chip ADC. Measuring the voltage within the semiconductor die, rather than measuring at external test points, provides a more accurate prediction of device operation. Multiple test points are measured using a multiplexer, multiple ADCs, or by reconfiguring an FPGA. Impedance versus frequency information of the greater power distribution system connected to the semiconductor die is obtained by transforming the voltage and current through the semiconductor die measured during a current discontinuity.

Power distribution system built-in self test using on-chip data converter

Method and apparatus for a bi-direction interface and communication link are described. More particularly, an input/output block is formed with a digitally controlled impedance output driver output coupled at an input/output node to an input terminal of a differential amplifier. Another terminal of the differential amplifier is used for inputting a reference voltage. As the digitally controlled impedance output buffer may be adjusted for impedance matching with transmission line impedance, no parallel terminating resistance is needed. Accordingly, two such input/output blocks may be coupled to form a bi-directional communication link with the advantage of an absence of parallel termination resistance at inputs to such input/output blocks.

Bi-directional interface and communication link

Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

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Boulder, CO, United States of America

Mark A Alexander