Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Mariusz Barczak

Piotr Wysocki

Kapil Karkra

Michal Wysoczanski

Sanjeev N Trika

Michael Mesnier

John Keys

Andrzej Jakowski

Shirish Dnyaneshware Bahirat

Arun Raghunath

Yi Zou

Luis Carlos Maria Remis

Daniel Robert McLeran

Slawomir Ptak

Ian F Adams

Maciej Kaminski

Wojciech Malikowski

Lay Wai Kong

Maksymilian Kunt

Dhruvil Shah

James Guilmart

Igor Konopko

Adam Rutkowski

An embodiment of an electronic apparatus may comprise a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory to determine a group of available types of persistent memory devices and a set of characteristics associated with each type of persistent memory device of the group of available types of persistent memory devices, determine of a set of requirements for a storage system, and determine a deployment configuration for the storage system with a lowest storage acquisition cost based on the group of available types of persistent memory devices, the sets of characteristics, and the set of requirements. Other embodiments are disclosed and claimed.

Multiple tier storage deployment management engine

High performance parity-based Redundant Array of Independent Disks (RAID) on Zoned Namespaces Solid State Drives (SSD)s with support for high queue depth write Input Output (IO) and Zone Append command is provided in a host system. The host system includes a stripe mapping table to store mappings between parity strips and data strips in stripes on the RAID member SSDs. The host system also includes a Logical to Physical (L2P) table to store data block addresses returned by the Zone Append command.

Method and apparatus to improve performance of a redundant array of independent disks that includes zoned namespaces drives

A host Flash Translation Layer (FTL) synchronizes host FTL operations with the drive FTL operations to reduce write amplification and over-provisioning. Embodiments of FTL synchronization map, at the host FTL software (SW) stack level, logical bands in which data is managed, referred to as host bands, to the physical bands on a drive where data is stored. The host FTL tracks validity levels of data managed in host bands to determine validity levels of data stored in corresponding physical bands, and optimizes defragmentation operations (such as garbage collection processes and trim operations) applied by the host FTL SW stack to the physical bands based on the tracked validity levels.

Reducing write amplification and over-provisioning using flash translation layer synchronization

In one embodiment, a system comprises a host processor and a storage system. The storage system comprises one or more storage devices, and each storage device comprises a non-volatile memory and a compute offload controller. The non-volatile memory stores data, and the compute offload controller performs compute tasks on the data based on compute offload commands from the host processor.

Computational data storage systems

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to receive a first request to allocate a direct swap file associated with an application stored in a system memory on a persistent storage media, and map a linear and continuous space of the persistent storage media to the direct swap file associated with the application in response to the first request. Other embodiments are disclosed and claimed.

Direct map memory extension for storage class memory

Dynamically controlled interrupt coalescing is performed by enabling interrupt coalescing when the queue depth of the submission queue is high and disabling interrupt coalescing when the queue depth of the submission queue is low to maintain a required quality of service for a solid state drive. The minimum number of completions in the completion queue to trigger an interrupt is modified based on the queue depth of the submission queue. The minimum number of completions is increased when there is an increase in the queue depth of the submission queue and decreased when there is a decrease in the queue depth of the submission queue.

Method and apparatus to perform dynamically controlled interrupt coalescing for a solid state drive

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.

Endurance aware data placement in storage system with multiple types of media

An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.

Stream classification based on logical regions

A host computing arrangement is provided, which may include a host processor having a host operating system and host kernel associated therewith. The host processor may be configured to host a guest operating system, mirror a filesystem of the guest operating system via the host kernel, and generate caching criteria by scanning the mirrored filesystem. The host computing arrangement may further include a cache engine. The cache engine may be configured to process an I/O request from the guest operating system based on the caching criteria generated by the host processor.

Host computing arrangement, remote server arrangement, storage system and methods thereof

Examples may include techniques to improve cache performance in a computing system. An eviction service may be used to manage a dirty list and a clean list, set a cache line to hot, set a cache line to clean, set a cache line to dirty, and evict a cache line from the cache. A cache engine may be used to write data into the cache at a cache line, request the eviction service to set the cache line to dirty, and manage a dirty cache lines counter for each chunk of the primary memory. A cleaning thread may be used to determine a dirtiest chunk of a primary memory, get a cache line of the dirtiest chunk, and when the cache line of the dirtiest chunk is dirty, read the cache line to get data from the cache, write the data to primary memory, request the eviction service to set the cache line to clean, and manage the dirty cache lines counters.

Method of dirty cache line eviction

A technology is described for a logical storage driver. An example method can include using the logical storage driver to: forward requests to a first storage stack for processing of an I/O workload associated with the I/O requests. Initiate generation of trace data for the I/O workload for collection and analysis to determine a second storage stack for improving performance of the I/O workload. Receive the storage processing logic for processing the I/O workloads using the storage configuration for the I/O workload, where the storage processing logic interfaces with the storage configuration. Intercept the I/O requests that correspond to the I/O workload. And, process the I/O workloads using the storage processing logic that interfaces with the storage configuration.

Logical storage driver

A method and apparatus for caching data accessed in a storage device, which include a selection of a list from a plurality of lists based on a cache block accessed from a cache memory, the cache memory being partitioned into a plurality of cache portions, each of the plurality of lists being assigned to a respective cache portion of the plurality of cache portions, each of the plurality of lists indicating an order in which cache blocks of the respective cache portion were accessed. Furthermore, a determination as to whether the accessed cache block meets a list update criteria, and an update the order in which cache blocks, assigned to the selected list, were accessed from the cache memory based on determining the accessed cache block meets the list update criteria may be included.

Least recently used-based hotness tracking mechanism enhancements for high performance caching

Examples may include techniques to monitor processing of I/O requests of an application being executed by a computing platform by collecting a trace of the I/O requests, the trace including an I/O class of each I/O request; replay the trace and automatically analyze possible cache configuration policies for using a cache during execution of the application by the computing platform; and determine an optimal cache configuration policy for the cache from the possible cache configuration policies. The optimal cache configuration policy may then be applied to use of the cache during subsequent execution of the application by the computing platform.

Cache utility modeling for automated cache configuration

Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to define a caching and processing priority policy for one or more input/output (I/O) request class types. The memory controller can monitor one or more I/O contexts of one or more I/O requests. The memory controller can associate the one or more I/O contexts with one or more I/O class types using an I/O context association table. The memory controller can execute the one or more I/O requests according to the caching and processing priority policy of the one or more I/O class types. The apparatus can include an interface to the memory controller.

Growing community of inventors

Gdansk, Poland

Mariusz Barczak