Texas Instruments Corporation

Marius Moe

Tarjei Aaberge

Tomas Motos

Wenxun Qiu

Bijit Thakorbhai Patel

Anand Ganesh Dabak

Espen Wium

Charles Sestok

Hagen Clemens Graf

Eivind Syvertsen

Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

Gated ring oscillator linearization

Using a phase interferometry method which utilizes both amplitude and phase allows the determination and estimation of multipath signals. To determine the location of an object, a signal that contains sufficient information to allow determination of both amplitude and phase, like a packet that includes a sinewave portion, is provided from a master device. A slave device measures the phase and amplitude of the received packet and returns this information to the master device. The slave device returns a packet to the master that contains a similar sinewave portion to allow the master device to determine the phase and amplitude of the received signals. Based on the two sets of amplitude and phase of the RF signals, the master device utilizes a fast Fourier transform or techniques like multiple signal classification to determine the indicated distance for each path and thus more accurately determines a location of the slave device.

Super resolution radio frequency location determination

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Time-to-digital converter stop time control

A technique of separating a sequence of modulation shift keying (MSK) symbols into a first portion and a second portion and separately comparing the first portion of the sequence of MSK symbols and the second portion of the sequence of MSK symbols against a first portion of a reference sequence of MSK symbols and a second portion of the reference sequence of MSK symbols allows a low complexity detection of a start field delimiter in a wireless communication packet.

Low-complexity synchronization header detection

Electronic devices and methods to provide wireless ranging are shown. A first electronic device includes a memory containing stored instructions that can perform a method for determining a distance between the first electronic device and a second electronic device. For each frequency in a selected set of frequencies, the method sets the transceiver to the respective frequency, sends a first tone having the frequency and a first phase to the second electronic device and receives a second tone having the first frequency and a second phase. For each selected frequency, the first electronic device determines the phase difference between the second tone and the controllable oscillator, receives a phase difference from the second electronic device, and calculates a phase delay for the frequency. The first electronic device calculates a phase delay difference for pairs of the frequencies; and determines the distance using these phase delay differences.

Electronic device and method for low power RF ranging

A communication apparatus comprising a plurality of signal processing units configured to perform a set of pre-determined signal processing functions according to a set of parameters, a plurality of programmable crossbars coupled to the plurality of signal processing units, and a plurality of control processors coupled to the plurality of programmable crossbars and configured to adjust the plurality of programmable crossbars to interconnect the signal processing units to implement a selected communication protocol, wherein at least one of the programmable crossbars routes data from a first of the plurality of signal processing units to a second of the plurality of signal processing units forming a data path without interception from the plurality of control processors.

Low power software defined radio (SDR)

An embodiment of the present disclosure provides a phase locked loop. A controllable oscillator generates a radio frequency (RF) signal. A divider is configured to produce a divided RF signal by dividing the RF signal by a division factor. A phase detection circuit is configured to receive a dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator. A dithering module is configured produce the dithered reference signal and the division factor, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and a target frequency of the RF signal.

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Fetsund, Norway

Marius Moe