Cyclos Semiconductor, Inc.

University of Michigan

Marios C Papaefthymiou

Alexander T Ishii

Conrad H Ziesler

Visvesh S Sathe

Jerry C Kao

Juang-Ying Chueh

Joohee Kim

A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks

A resonant clock distribution network architecture is proposed that uses clock drivers of programmable size and reference clocks of programmable duty cycle to achieve a target clock rise time and clock amplitude with low energy consumption when operating in any one of multiple clock frequencies in resonant or non-resonant mode. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Resonant clock distribution network architecture with programmable drivers

An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Architecture for controlling clock characteristics

An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels.

Architecture for operating resonant clock network in conventional mode

A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).

Resonant clock and interconnect architecture for digital devices with multiple clock networks

An architecture for resonant clock distribution networks is proposed. This architecture allows for the energy-efficient operation of a resonant clock distribution network at multiple clock frequencies through the deployment of flip-flops that can be selectively enabled. The proposed architecture is primarily targeted at the design of resonant clock networks with integrated inductors and exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Architecture for frequency-scaled operation in resonant clock distribution networks

An inductor architecture for resonant clock distribution networks is proposed. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture is primarily targeted at the design of integrated inductors and exhibits relatively low area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Architecture for adjusting natural frequency in resonant clock distribution networks

A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Architecture for single-stepping in resonant clock distribution networks

An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead

Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Clock distribution network architecture with clock skew management

Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.

Clock distribution network architecture for resonant-clocked systems

Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.

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Ann Arbor, MI, United States of America

Marios C Papaefthymiou