Infineon Technologies Ag

Marion Nichterwitz

Klaus Goller

Olaf Heitzsch

Alexander Ruf

An integrated circuit arrangement is disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement. The auxiliary indentation contains a metal through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation serves as an alignment mark during the production of the integrated circuit arrangement.

Integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks

A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.

Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement

A method for producing a metal layer with a given thickness includes the step of measuring an electrical resistance of the metal layer via connections on a starting layer provided under the metal layer. The resistance measurement is performed during or after the deposition of the metal layer. The layer thickness of the deposited metal layer is determined from the resistance measurement. Depending on the thickness of the already deposited metal layer, the deposition process is continued or repeated until a metal layer with a desired thickness is produced.

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Dresden, Germany

Marion Nichterwitz