Hughes Aircraft Company

Other

Marion D Clark

William E Stanchina

K Vaidyanathan

Deborah J Jackson

C Lawrence Anderson

A heterojunction bipolar transistor (HBT) is formed with self-aligned base-emitter and base-collector junctions by forming a two-level mask over a doped base layer, sequentially forming openings in registration through the two mask layers, and using the opening in one mask layer to define the collector region and the opening in the other mask layer to define the emitter. A buried conductive layer formed by a dopant implant establishes an electrical contact to the collector region, and connects to the surface via another conductive implant that extends through a lateral extension of the collector region. The collector region itself is formed by a dopant implant, while the active base region which forms junctions with the emitter and collector is thinner than the remainder of the base layer; the latter feature reduces the resistivity associated with connections to lateral base contacts. Parasitic capacitances are minimized when the collector and buried conductive layers are implanted into a semi-insulating substrate such that only the active junction regions overlap.

Self-aligned, planar heterojunction bipolar transistor

A heterojunction bipolar transistor (HBT) is formed with self-aligned base-emitter and base-collector junctions by forming a two-level mask over a doped base layer, sequentially forming openings in registration through the two mask layers, and using the opening in one mask layer to define the collector region and the opening in the other mask layer to define the emitter. A buried conductive layer formed by a dopant implant establishes an electrical contact to the collector region, and connects to the surface via another conductive implant that extends through a lateral extension of the collector region. The collector region itself is formed by a dopant implant, while the active base region which forms junctions with the emitter and collector is thinner than the remainder of the base layer; the latter feature reduces the resistivity associated with connection to lateral base contacts. Parasitic capacitances are minimized when the collector and buried conductive layers are implanted into a semi-insulating substrate such that only the active junction regions overlap.

Self-aligned, planar heterojunction bipolar transistor and method of

An optical waveguide is established near the surface of a body of bulk, optically transparent, crystalline material (12) by depositing and bonding a thin layer of material (16) that undergoes an irreversible structural transition under annealing such as silicon nitride or silicon oxide on a surface of the bulk crystalline material (12). The assembly is then heated to change the state of the thin layer and produce stress on the order of 10.sup.10 to 10.sup.11 dynes per square centimeter or more. Open guideways or breaks (22, 24) are then formed in the thin layer (16), thereby establishing optical stress waveguides (32, 34) in the bulk crystalline material (12), just under the open guideways. The bulk crystalline material is then employed for modulation, detection or in other interactive processes with respect to optical signals applied to the waveguide.

Stress waveguides in bulk crystalline materials

The specification describes a planar gallium arsenide charge coupled device and process for making same wherein a first series of metal pattern forming steps are performed on the surface of a GaAs semiconductor body to form input, output and bias electrodes of a CCD in a first level or plane of the structure. In a subsequent, second series of metal pattern forming steps, a plurality of charge transfer electrodes are formed between the CCD input and output electrodes, and simultaneously an annular charge isolation electrode is deposited so as to completely surround the input, output, and charge transfer electrodes of the CCD. These electrodes deposited in this second series of metal pattern forming steps lie in a second level or plane of the structure being fabricated. Next, a dielectric mask is formed on the surface of the last named electrodes. Openings ('vias') are formed therein which are aligned with the input, output, charge transfer and charge isolation electrodes. Thereafter, a third series of metal pattern forming steps are utilized to form a plurality of crossover or lead-in electrodes which are deposited in the above openings in the dielectric mask to provide electrical signal and bias coupling to the electrodes formed in the above first and second series of metal pattern forming steps. Thus, by forming the charge isolation electrode simultaneously with the electrodes of the charge coupled device per se, the total number of device fabrication steps are minimized.

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Newbury Park, CA, United States of America

Marion D Clark