Intel Corporation

Lantiq Beteiligungs Gmbh & Co. Kg

Lantiq Deutschland Gmbh

Mario Traeber

Juraj Povazanec

Chee Kiang Goh

Chee-kiang Goh

Biju Sukumaran

Examples include a method of identifying single twisted pair cable Ethernet auto-negotiation requests or double twisted pair cables Ethernet auto-negotiation requests using detection of message time interval patterns. The method includes receiving, by a first Ethernet device, a plurality of messages transmitted by a second Ethernet device over a single twisted pair cable connecting the first Ethernet device and the second Ethernet device; storing one or more time intervals between starting times of successive pairs of the plurality of messages; determining if a pattern is found in the time intervals; when the pattern is found, setting a single twisted pair cable communications mode between the first Ethernet device and the second Ethernet device; and performing priority resolution between the first Ethernet device and the second Ethernet device.

Method of ethernet auto-negotiation over one cable

A device comprises a clock source configured to provide a spread-spectrum modulated clock signal and a control signal associated with the spread-spectrum modulated clock signal. The device also comprises a circuitry configured to receive the spread-spectrum modulated clock signal, to receive the control signal, and to sample a data signal in accordance with the spread-spectrum modulated clock signal and the control signal.

Spread-spectrum modulated clock signal

A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.

Method and apparatus for preventing inherent error propagation of successive approximation register analog-to-digital converter through digital correction

According to one embodiment, an Ethernet communication device is configured to be connected to one or more twisted-pair links, each twisted-pair link having a particular capacity. The Ethernet communication device includes a physical interface transceiver. The physical interface transceiver sets a data transmission rate of the Ethernet communication device based on a total capacity of the twisted-pair links connected to the Ethernet communication device. The physical interface transceiver transmits data over the twisted-pair links connected to the Ethernet communication device at the data transmission rate.

Multi-mode ethernet transceiver

A method and a corresponding device for providing a delay value of a communication electronic unit. A digital input signal is delayed by a delay element. The input and the output signals of the delay element are sampled and the sampled signals are compared. A mismatch counter is incremented when the amplitudes of the sampled signals are not equal and a signal transition counter N is incremented when the input signal transitions. The provided delay value is proportional to the mismatch counting value, proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value.

Probabilistic digital delay measurement device

According to one embodiment, an Ethernet physical interface transceiver comprises a link interface configured to be segmented into one or more active ports. First circuitry is configured to transmit and receive data either at a relatively high data rate via a single active port of the link interface when the transceiver is configured in a first mode or at a relatively low data rate via at least two different active ports of the link interface when the transceiver is configured in a second mode. Second circuitry is configured to communicate with a media access controller either at a relatively high data rate when the transceiver is configured in the first mode or at a relatively low data rate when the transceiver is configured in the second mode. Clock circuitry is configured to independently synchronize operation of each active port of the link interface.

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Singapore, Singapore

Mario Traeber