Space Exploration Technologies Corp.

Stmicroelectronics (grenoble 2) Sas

Mario Toma

Andras Tantos

David Francois Jacquet

Didier Fuin

Arthur Stoutchinin

In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a first reference clock signal and generate a first reference time signal based on the timing signal and the first reference clock signal. The IC chip is configured to generate a second reference time signal based on the first reference time signal and a second reference clock signal, different from the first reference clock signal The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The IC chip is configured to synchronize one or more actions performed by the IC chip based on one or more of the first reference time signal or the second reference time signal.

Chip to chip time synchronization

In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. Each of the first, second, and third reference time signals is associated with a count of a number of cycles of the reference clock signal starting from a same particular cycle of the reference clock signal.

An electronic system implements a software application described in the form of a graph of the Kahn network type, and includes actors. At least one of the actors includes a processor, and at least another one of the actors includes a hardware accelerator. Buffer memories are coupled between the actors. A central processor is configured to enable communications between the actors according to a communications and synchronization protocol. The processor and the hardware accelerator are configured to use different individual communications protocols.

Growing community of inventors

Grenoble, France

Mario Toma