Intersil Americas Inc.

Other

Intersil Corporation

Mario Sanchez

Kantilal Bacrania

Bang-Sup Song

J Mikko Hakkarainen

Eric C Sung

Hsin-Shu Chen

Brian L Allen

Gregory J Fisher

Patrick S Kochie

Thomas R Richmond

Donald A Ouach

In one embodiment, the present invention describes a gate closure system having a barrier or gate operator for moving a gate between a gate fully opened position and a gate fully closed position. The gate closure system preferably further includes, among other things, a master control board with input and output points to receive and transmit data associated with movement of the gate, including a panic control override mode circuit input to the master control board that negates all gate movement parameters during any portion of the gate's travel path to open or close the gate at a substantially greater rate of speed than typically used to open or close the gate during normal operation, regardless of the gate's speed, torque, direction of travel (forward or backward), or whether the gate is stationary.

Barrier operator with panic control override mode and related method

A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS&mdash;VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

Track and hold with dual pump circuit

A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

System and method of DC calibration of amplifiers

A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

Calibration of resistor ladder using difference measurement and parallel resistive correction

A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

Analog to digital converter using subranging and interpolation

A digital-to-analog converter (DAC) includes a plurality of current sources on a substrate operable in a predetermined sequence of use for generating an output current based upon a digital input, and a connection network for establishing the predetermined sequence of use for the current sources based upon the actual current values and to increase performance of the DAC. For example, the predetermined sequence of use can be set to reduce integral non-linearity error of the DAC. The connection network may be provided by a plurality of fusible links selectively connected to set the predetermined sequence of use. The current sources may include a first group of most significant bit (MSB) current sources for a predetermined number of MSBs. In addition, the plurality of current sources may include a second group of mid-most significant bit (mid MSBs) current sources for a predetermined number of mid MSBs. The plurality of current sources have actual values sortable from lowest to highest, and each actual current value will define an error value with both a magnitude and polarity relative to the desired value. One embodiment for sorting the order of use of the current sources is based upon the error values.

Digital-to-analog converter including current sources operable in a

An analog-to-digital converter (ADC) includes a plurality of capacitors formed on a semiconductor substrate and having actual capacitance values statistically related to desired capacitance values, and a gain stage comprising an amplifier and capacitors selected to provide a more accurate gain for the gain stage. A first at least one capacitor is connected between an input and an output of the amplifier defining a feedback capacitance, and a second at least one capacitor is connected between the input of the amplifier and an input of the at least one gain stage defining an input capacitance. In addition, the ADC includes a connection network selectively connecting the first at least one capacitor and the second at least one capacitor from among the plurality of capacitors to provide a desired ratio of feedback capacitance to input capacitance based upon the actual capacitance values. Accordingly, a gain can be set for the gain stage that is more accurate than would otherwise be obtained. The high accuracy switched capacitor gain stage may be used in other applications.

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Palm Bay, FL, United States of America

Mario Sanchez