Kioxia Corporation

Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Mario Sako

Yoshihiko Kamata

Koji Kato

Kosuke Yanagidaira

Mai Shimizu

Tsukasa Kobayashi

Takuyo Kodama

Yoko Deguchi

Takahiro Suzuki

Masahiro Yoshihara

Yasuhiko Honda

Naofumi Abiko

Toshifumi Watanabe

Noriyasu Kumazaki

Hiromitsu Komai

Keita Kimura

Tomoyuki Hamano

Kenri Nakai

Koji Tabata

Yuko Yokota

Jun Fujimoto

A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Semiconductor storage device

A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.

Semiconductor memory

A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through the second and third transistors.

A semiconductor storage device includes a bit line, a memory cell transistor electrically connected to the bit line, and a sense amplifier that reads data from the memory cell transistor via the bit line. During an operation of determining first data and second data, while continuously applying a first voltage to a gate of the memory cell transistor, the sense amplifier first determines the first data based upon a second voltage, and then determines the second data based upon a third voltage lower than the second voltage.

According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, and a sense amplifier. The sense amplifier includes: a first node configured to be electrically coupled to the bit line; a first transistor in which a gate is coupled to the first node, and which is configured to be coupled to a second node; a second transistor configured to couple the second node and a third node; and a third transistor in which a gate is coupled to the third node, and which is configured to be coupled to the first node. The sense amplifier applies a second voltage obtained by amplifying a first voltage of the first node to the third node, and applies a third voltage obtained by amplifying the second voltage to the first node.

Semiconductor memory device

A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.

A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through its second and third transistors.

According to one embodiment, a semiconductor memory device includes: a first bit line; a first memory cell electrically coupled to the first bit line; and a first sense amplifier configured to sense and store data read out to the first bit line. The first sense amplifier includes a first latch circuit and a second latch circuit. In a program operation, each of the first and second latch circuits stores any one bit of program data. In a first verify operation, data is exchanged between the first latch circuit and the second latch circuit when performing the first verify operation for a first data.

A semiconductor memory device includes a word line connected to memory cells, bit lines respectively connected to the memory cells, and a control circuit configured to control voltages applied to the word line and the bit lines during a write operation. When writing data into a target memory cell, the control circuit executes first and second loops in sequence. In executing the first loop, the control circuit applies a first program voltage to the word line during the program operation, and applies a verify voltage to the word line during the verify operation, and upon detecting that the verify operation neither passed nor failed, the control circuit selects one of two pass write voltages to be applied to the bit line connected to the target memory cell during the program operation of the second loop according to a sequential position of the first loop in the sequence of loops.

A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.

A semiconductor memory cell includes a memory cell, a word line and a source line both connected to the memory cell, and a control circuit. During a read operation on the memory cell, the control circuit applies a first voltage to the word line, applies a second voltage greater than the first voltage to the word line, and then applies a third voltage which is greater than the first voltage and smaller than the second voltage to the word line. During the read operation on the memory cell, the control circuit also applies a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and then applies a fifth voltage smaller than the fourth voltage to the source line.

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Yokohama Kanagawa, Japan

Mario Sako