Sgs-Thomson Microelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Stmicroelectronics S.r.l.

Stmicroelectronics Gmbh

Sgs-Thomson Microelectronics Limited

Mario Paparo

Sergio Palara

Raffaele Zambrano

William A Phillips

Santo Puzzolo

Davide Giuseppe Patti

Natale Aiello

Piero Capocelli

Domenico Rossi

Roberto Pelleriti

Michele Zisa

Roberto Pellicano

Giovanni Cali&prime;

Massimiliano Belluso

Giuseppe Palmisano

Guglielmo Sirna

DavideGiuseppe Patti

Roberto Pellicano'

The pressure in the combustion chamber of an electronically controlled spark plug ignition engine may be estimated in real time mode without specific sensors by processing sensed ionization current data to calculate features of the current waveform proven to be correlated to the pressure inside the engine cylinders and correlating them on the basis of a look up table of time invariant correlation coefficients generated through a calibration campaign of tests on a test engine purposely equipped with sensors. A mathematical model of the electrical and physical spark plug ignition system and combustion chamber of the engine is refined during calibration by iteratively testing the interactive performance of correlation coefficients of related terms of a mathematical expression of the model and comparing the expressed pressure value with the real pressure value as measured by a sensor.

Method and processing system of sensed ionization current data for real time estimate of combustion chamber pressure in a spark ignition engine

Method and processing system of sensed ionization current data for real time estimation of combustion chamber pressure in a spark ignition engine

A spark plug, including an insulator embedding a first metallic electrode axially extending therethrough from a high voltage outer end terminal to the center of the inner end of the insulator from which it protrudes; a metallic ground electrode isolated from the first electrode and having an extended inner termination facing toward the first electrode extending from the insulator tip for defining therebetween a spark gap, a resistive element connected to the ground electrode such that upon mounting the spark plug in an internal combustion engine, the ground electrode electrically connects to the engine body through the resistive element; and a second outer termination of the ground electrode, adapted to constitute an accessible sensing terminal.

Enhanced method of sensing ionization current in spark ignition internal combustion engines and related spark plug structures

A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.

Delay circuit and method

Presented is a low-drop type of voltage regulator formed with BiCMOS/CMOS technology. The regulator includes an input terminal that receives a stable voltage reference connected to one input of an operational amplifier through a switch controlled by a power-on enable signal. A supply voltage reference powers the operational amplifier. The regulator includes an output transistor connected to an output of the amplifier to generate a regulated voltage value to be fed back to the amplifier input. A second transistor is connected in series between the output transistor and the supply voltage reference. The regulator uses a control circuit portion connected between the control terminal of the second transistor and the supply voltage reference to prevent the breakdown of the output transistor from occurring.

Low drop BiCMOS/CMOS voltage regulator

A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the voltage of a CMOS-logic circuit portion, a dynamic level shifting circuit interposed between the input stage and the output stage, the output stage being connected to the CMOS-logic circuit portion.

High-speed bipolar-to-CMOS logic converter circuit

A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

Method for forming an integrated emitter switching configuration using

A high-side gate driving circuit, where a current-mode differential error amplifier is used to regulate the current sourced to the gate. A current path is provided from the gate to the source of the power device, and a constant current is provided to the gate. A variable current source is also provided, and this current source is controlled by the output of the error amplifier. Preferably a voltage offset (avalanche breakdown diode) is interposed between the gate and source of the high-side driver; this ensures that the feedback loop will operate in a bistable mode, which avoids instability problems.

High-side-driver gate drive circuit

Integrated emitter switching configuration using bipolar transistors

A high current MOS transistor integrated bridge structure includes at least two arms, each having a first and a second MOS transistor. The structure is formed on an N++ substrate forming a positive potential output terminal, and an N-type epitaxial layer. For each first transistor, an L shaped region is formed of a horizontal N+ region which is connected to the surface through an N++ vertical region. Forming a corresponding alternating current input with this region is an N type region which has within it a succession of P type regions, and a pair of N+ type regions forming a negative potential output terminal. For each second transistor, an N+ region has N++ lateral regions extending to the surface, and includes an N type region containing a succession of P type regions and a pair of N+ regions forming corresponding alternating current inputs. The first transistor of each arm is entirely contained within a P type isolation region which has P+ regions extending to the surface of the substrate.

High current MOS transistor bridge structure

An integrated bridge device includes at least two arms, each of which is formed of a first and second diode connected transistor in series. The device is formed in an N+ substrate, which forms a positive output terminal. N- and N type epitaxial layers are formed over the substrate, and P and P+ regions are formed therein for each of the aforesaid arms. An N type region is contained within the P and P+ regions, and in turn contains a P type region forming a negative potential output terminal. Also included in the N type region are N++ regions capable of minimizing the current gain of parasitic transistors formed within the device.

Integrated bridge device for optimizing conduction power losses

In accordance with the present invention, the above and other objects and advantages are obtained with a bootstrap circuit for a power MOS transistor in a high side configuration. Such circuit includes a first capacitor chargeable to a first voltage which is a function of the supply voltage of the power transistor. It further includes a second capacitor combined with the first capacitor so as to provide a second voltage which is higher than the first voltage and the threshold voltage of the power transistor.

Bootstrap circuit for driving a power MOS transistor

A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N-epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

A device accomplishes protection against breakdown of an N+ type diffused region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffused region (6). The diffused region (6) is insulated electrically with respect to the P type containment region (5).

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San Giovanni la Punta, Italy

Mario Paparo