Agilent Technologies, Inc.

Mario Martinez

Vamsi K Srikantam

A flip-flop having a sleep mode in which power consumption is reduced. The flip-flop comprises a clock input, a data input, an input stage, an input gate, an output stage and an output clamp. The input gate is interposed between the data input and the input stage and operates in the sleep mode to isolate the input stage from the data input. The output stage is coupled to the input stage and includes an output having a first output state and a second output state. The output clamp operates in the sleep mode to set the output stage to a predetermined state regardless of the data states at the data input and the clock input. The predetermined state is the one of the output states in which the leakage power consumption of the flip-flop is less than in the other of the output states. The predetermined state may alternatively be the one of the output states in which the leakage power consumption of circuitry connected to the output of the flip-flop is less than in the other of the output states. As a further alternative, the predetermined state may be the one of the output states in which the leakage power consumption of a digital electronic circuit of which the flip-flop forms part is less than in the other of the output states.

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Stanford, CA, United States of America

Mario Martinez